Page 1
SN74ALS29841
10-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS149A – JUNE 1988 – REVISED JANUARY 1995
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Bus-Structured Pinout
• Provides Extra Bus-Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
• Buffered Control Inputs Reduce dc Loading
Effects
• Power-Up High-Impedance State
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
DW OR NT PACKAGE
(TOP VIEW)
OE
1
24
1D
2
23
2D
3
22
3D
4
21
4D
5
20
5D
6
19
6D
7
18
7D
8
17
8D
9
16
9D
10
15
10D
11
14
GND
12
13
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE
This 10-bit latch features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The ten latches are transparent D-type latches. The SN74ALS29841 has noninverting data (D) inputs.
A buffered output-enable (OE
) input can place the ten outputs in either a normal logic state (high or low logic
levels) or in a high-impedance state. The outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE
does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN74ALS29841 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
LLX Q
HXX Z
OUTPUT
Q
0
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
Page 2
SN74ALS29841
10-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS149A – JUNE 1988 – REVISED JANUAR Y 1995
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
9D
10D
1
13
2
3
4
5
6
7
8
9
10
11
EN
C1
1D
logic diagram (positive logic)
1
OE
23
22
21
20
19
18
17
16
15
14
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
13
LE
1D
C1
2
1D
To Nine Other Channels
23
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
SN74ALS29841
VOHV
V
V
10-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS149A – JUNE 1988 – REVISED JANUARY 1995
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
t
w
t
su
t
h
T
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –24 mA
Low-level output current 48 mA
Pulse duration, LE high 6 ns
Setup time, data before LE↓ 2.5 ns
Hold time, data after LE↓ 4.5 ns
Operating free-air temperature 0 70 °C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
I
OS
I
CC
‡
VCC = 4.75 V, II = –18 mA –1.2 V
= 4.75
CC
VCC = 4.75 V, IOL = 48 mA 0.35 0.5 V
VCC = 5.25 V, VO = 2.7 V 20 µA
VCC = 5.25 V, VO = 0.4 V –20 µA
VCC = 5.25 V, VI = 5.5 V 0.1 mA
VCC = 5.25 V, VI = 2.7 V 20 µA
VCC = 5.25 V, VI = 0.4 V –0.2 mA
VCC = 5.25 V, VO = 0 –75 –250 mA
VCC = 5.25 V, Outputs low 55 85 mA
IOH = –15 mA 2.4 3.3
IOH = –24 mA 2 3.1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN74ALS29841
(INPUT)
(OUTPUT)
D
A
Q
C
50 pF
ns
D
A
Q
C
300 pF
ns
LE
A
Q
C
F
ns
LE
A
Q
C
300 pF
ns
OE
A
Q
C
50 pF
ns
OE
A
Q
C
300 pF
ns
OE
A
Q
C
F
ns
OE
A
Q
C
F
ns
10-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SDAS149A – JUNE 1988 – REVISED JANUAR Y 1995
switching characteristics (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PLZ
FROM
TO
ny
ny
ny
ny
ny
ny
ny
ny
TEST CONDITIONS
=
L
=
L
= 50 p
L
=
L
=
L
=
L
= 50 p
L
p
= 5 p
L
VCC = MIN to MAX†,
TA = MIN to MAX
MIN MAX
2 9.5
2 9.5
14
14
12
12
16
16
14
14
20
23
15
12
†
UNIT
9
9
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
10-BIT BUS-INTERFACE D-TYPE LATCH
SDAS149A – JUNE 1988 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SN74ALS29841
WITH 3-STATE OUTPUTS
From Output
Under Test
(see Note A)
Timing Input
Data Input
Input
In-Phase
Output
Out-of-Phase
Output
t
PLH
t
PHL
Test Point
C
L
t
su
SETUP AND HOLD TIMES
R1
1 kΩ
LOAD CIRCUIT
VOLTAGE WAVEFORMS
1.5 V 1.5 V
1.5 V 1.5 V
All Diodes
1N916 or 1N3064
1.5 V
S1
t
1.5 V1.5 V
h
1.5 V1.5 V
S2
t
PHL
t
PLH
V
RL = 180 Ω
3 V
0
3 V
0
3 V
0
V
OH
V
OL
V
OH
V
OL
CC
High-Level
Pulse
Low-Level
Pulse
Output
Control
Waveform 1
(see Note B)
Waveform 2
(see Note B)
SWITCH POSITION TABLE
TEST S1 S2
Closed
Closed
Open
Closed
Closed
Closed
1.5 V
t
w
1.5 V
PULSE DURATIONS
1.5 V
t
PHZ
1.5 V
t
PZL
t
PZH
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
VOLTAGE WAVEFORMS
Closed
Closed
Closed
Open
Closed
Closed
1.5 V
1.5 V
1.5 V1.5 V
t
PLZ
3 V
0
3 V
0
0.5 V
0.5 V
3 V
0
≈ 4.5 V
≈ 1.5 V
V
OL
V
OH
≈ 1.5 V
≈ 0
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
5
Page 6
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...