Page 1
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
CLK
SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS119D – FEBRUARY 1987 – REVISED JANUAR Y 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Functionally Similar to AMD’s AM29833
• High-Speed Bus Transceiver With Parity
Generator/Checker
• Parity-Error Flag With Open-Collector
Outputs
• Register for Storing the Parity-Error Flag
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) 300-mil DIPs
description
The SN74ALS29833 is an 8-bit to 9-bit parity
transceiver designed for two-way communication
between data buses. When data is transmitted
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error
(ERR
) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs
can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (P ARITY) output and monitors the parity of the I/O ports
with an open-collector ERR
flag. ERR is clocked into the register on the rising edge of the clock (CLK) input.
The error-flag register is cleared with a low pulse on the clear (CLR
) input. When both OEA and OEB are low,
data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error
condition that gives the designer more system diagnostic capability.
The SN74ALS29833 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
OEB OEA CLR
CLK
Ai
∑ of Hs
Bi
†
∑ of Ls
A B PARITY
ERR
‡
FUNCTION
Odd
L
p
LHX
X
Even
NANAAHNA
A data to B bus and generate parit
y
Odd
H
p
HLH↑NA
Even
BNANALB data to A bus and check parit
y
X X L X X X X NA NA H Clear error-flag register
H No↑ X NC
LNo↑ X
H
H
H
H ↑ Odd
XZZ
Z
H
Isolati
on
§
H ↑ Even L
Odd
H
A data to B bus and generate inverted
LLX
X
Even
NANAALNA
g
parity
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume ERR
was previously high.
§
In this mode, ERR
, when clocked, shows inverted parity of the A bus.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Page 2
SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS119D – FEBRUAR Y 1987 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
8x
EN
A1–A8
OEA
OEB
CLK
CLR
G1
1
1
1
1
MUX
2K
EN
8x
B1–B8
PARITY
ERR
88
8
8
8
9
P
R
C1
1D
14
1
13
11
15
10
2–9 16–23
error-flag waveforms
ERR
CLR
CLK
Bi + PARITY
OEA
OEB
Even
H
Odd
L
H
L
H
L
H
L
H
L
t
su
t
PLH
t
w
t
w
t
h
t
su
t
PHL
Page 3
SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS119D – FEBRUARY 1987 – REVISED JANUAR Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ERROR-FLAG FUNCTIONS
INPUTS
INTERNAL
TO DEVICE
OUTPUT
PRESTATE
OUTPUT
FUNCTION
CLR CLK
POINT P
ERR
n–1
†
ERR
H ↑ H H H
H ↑ X L L
Sample
H ↑ L X L
L X X X H Clear
†
ERR
n–1
represents the state of ERR
before any changes at CLR, CLK, or point P .
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled I/O port 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN MAX UNIT
V
CC
Supply voltage 4.75 5.25 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
OH
High-level output voltage, ERR 5.5 V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 48 mA
CLK high 10
t
w
Pulse duration
CLK low 10
ns
CLR low 10
Bi and PARITY 17
t
su
S
etup time before
CLK↑
CLR inactive 15
ns
t
h
Hold time, Bi and PARITY after CLK↑ 0 ns
T
A
Operating free-air temperature 0 70 °C
Page 4
SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS119D – FEBRUAR Y 1987 – REVISED JANUAR Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.75 V , II = –18 mA –1.2 V
IOH = –15 mA 2.4
V
OH
All I/O
s except
ERR
V
CC
=
4.75 V
IOH = –24 mA 2
V
I
OH
ERR VCC = 4.75 V , VOH = 5.5 V 0.1 mA
V
OL
VCC = 4.75 V , IOL = 48 mA 0.35 0.5 V
I
I
VCC = 5.25 V , VI = 5.5 V 0.1 mA
I
IH
‡
VCC = 5.25 V , VI = 2.7 V 20 µA
Data
–0.2
I
IL
‡
Control
V
CC
= 5.25 V,
V
I
= 0.4
V
–0.75
mA
I
O
§
VCC = 5.25 V , VO = 0 –75 –250 mA
I
CC
VCC = 5.25 V 70 100 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics (see Figure 1)
PARAMETER
FROM
TO
TEST CONDITIONS
VCC = 4.75 V to 5.25 V,
TA = MIN to MAX
¶
UNIT
(INPUT)
(OUTPUT)
MIN MAX
t
PLH
8
t
PHL
A or B
B
or
A
C
L
= 50 p
F
8
ns
t
PLH
15
t
PHL
A or B
B
or
A
C
L
=
300 pF
15
ns
t
PLH
15
t
PHL
A
PARITY
C
L
= 50 p
F
19
ns
t
PLH
22
t
PHL
A
PARITY
C
L
=
300 pF
24
ns
t
PZH
17
t
PZL
OEA
or
OEB
A
or
B
C
L
= 50 p
F
17
ns
t
PZH
23
t
PZL
OEA
or
OEB
A
or
B
C
L
=
300 pF
23
ns
t
PHZ
9
t
PLZ
OEA
or
OEB
A
or
B
C
L
= 5 p
F
9
ns
t
PHZ
15
t
PLZ
OEA
or
OEB
A
or
B
C
L
= 50 p
F
8
ns
t
PHL
CLK
ERR CL = 50 pF
13 ns
t
PLH
CLR
ERR CL = 50 pF
13 ns
t
PLH
17
t
PHL
OEA
PARITY
C
L
= 50 p
F
19
ns
t
PLH
p
22
t
PHL
OEA
PARITY
C
L
=
300 pF
25
ns
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Page 5
SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SDAS119D – FEBRUARY 1987 – REVISED JANUAR Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT 1
ALL OUTPUTS EXCEPT FOR ERROR FLAG
R1
1 kΩ
All Diodes
1N916 or 1N3064
From Output
Under Test
Test Point
S2
C
L
(see Note A)
RL = 180 Ω
1.5 V
1.5 V
1.5 V
3 V
3 V
0
0
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
Data Input
1.5 V
1.5 V
3 V
3 V
0
0
High-Level
Input
Low-Level
Input
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
t
PHL
t
PLH
t
PLH
t
PHL
Out-of-Phase
Output
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHZ
t
PLZ
0.5 V
t
PZL
t
PZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0
Output
Control
Waveform 1
(see Note B)
Waveform 2
(see Note B)
≈ 0
V
OH
V
OL
≈ 1.5 V
0.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
V
CC
S1
SWITCH POSITION TABLE
TEST S1 S2
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
≈ 4.5 V
≈ 1.5 V
Input
V
CC
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT 2
ERROR-FLAG OUTPUT
180 Ω
510 Ω
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuits and Voltage Waveforms
Page 6
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Copyright 1998, Texas Instruments Incorporated
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