Datasheet SN74ALS29823DW, SN74ALS29823DWR, SN74ALS29823NT, SNJ54ALS29823JT Datasheet (Texas Instruments)
Page 1
SN54ALS29823 . . . JT PACKAGE
SN74ALS29823 . . . DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Functionally Equivalent to AMD’s AM29823
• Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
• Outputs Have Undershoot-Protection
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce dc Loading
Effects
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (NT) and Ceramic (JT) 300-mil DIPs
description
These 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O
ports, bidirectional bus drivers, parity bus interfacing, and working registers.
With the clock-enable (CLKEN
) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high
transitions of the clock (CLK) input. Taking CLKEN
high disables the clock buffer, latching the outputs. The
′ALS29823 have noninverting data (D) inputs. Taking the clear (CLR
) input low causes the nine Q outputs to
go low independently of the clock.
A buffered output-enable (OE
) input places the nine outputs in either a normal logic state (high or low logic levels)
or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down
conditions. The outputs remain in the high-impedance state while the device is powered down. In the
high-impedance state, the outputs neither load nor drive the bus lines significantly . The high-impedance state
and increased drive provide the capability to drive bus lines without interface or pullup components.
OE
does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS29823 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS29823 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLR CLKEN CLK D
Q
L L X X X L
L HL↑HH
LHL↑LL
LHHXX Q
0
HXXXX Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Page 2
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
EN
1
7
6D
8
7D
9
8D
10
9D
2D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
13
CLK
1C2
R
11
CLR
G1
14
CLKEN
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
To Eight Other Channels
23
2
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE
CLR
Page 3
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled high-impedance output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS29823 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS29823
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –18 mA
I
OL
Low-level output current 32 mA
CLR low 7
twPulse duration
CLK high or low 8
ns
CLR inactive 7
t
su
Setup time before CLK↑
Data
4
ns
CLKEN high or low 8
CLKEN 2
t
h
Hold ti
me after
CLK↑
Data 4
ns
T
A
Operating free-air temperature –55 25 125 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS29823
PARAMETER
TEST CONDITIONS
MIN TYP‡MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
IOH = –12 mA 2.4 3.3
VOHV
CC
=
4.5 V
IOH = –18 mA 2
V
V
OL
VCC = 4.5 V, IOL = 32 mA 0.25 0.5 V
I
OZH
VCC = 5.5 V, VO = 2.4 V 50 µA
I
OZL
VCC = 5.5 V, VO = 0.4 V –50 µA
I
I
VCC = 5.5 V, VI = 5.5 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.5 mA
I
OS
§
VCC = 5.5 V, VO = 0 –75 –250 mA
Outputs high 90
I
CC
VCC = 5.5 V
Outputs low 105
mA
Outputs open 115
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Page 4
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
FROM TO
VCC = MIN to MAX†,
TA = MIN to MAX
†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN54ALS29823
UNIT
MIN MAX
t
PLH
2 11.5
t
PHL
CLK
A
ny
Q
C
L
=
50 pF
2 11.5
ns
t
PLH
2 21
t
PHL
CLK
A
ny
Q
C
L
=
300 pF
2 21
ns
t
PHL
CLR Any Q CL = 50 pF 1 17.5 ns
t
PZH
1 17
t
PZL
OE
A
ny
Q
C
L
= 50 p
F
1 17
ns
t
PZH
1 25
t
PZL
OE
A
ny
Q
C
L
=
300 pF
1 29.5
ns
t
PHZ
1 16
t
PLZ
OE
A
ny
Q
C
L
= 50 p
F
1 14
ns
t
PHZ
p
1 12
t
PLZ
OE
A
ny
Q
C
L
= 5 p
F
1 11
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN74ALS29823 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS29823
MIN NOM MAX
UNIT
V
CC
Supply voltage 4.75 5 5.25 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –24 mA
I
OL
Low-level output current 48 mA
CLR low 5
twPulse duration
CLK high or low 5
ns
CLR inactive 5
t
su
Setup time before CLK↑
Data
2
ns
CLKEN high or low 6
CLKEN 0
t
h
Hold ti
me after
CLK↑
Data 2
ns
T
A
Operating free-air temperature 0 25 70 °C
Page 5
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS29823
PARAMETER
TEST CONDITIONS
MIN TYP†MAX
UNIT
V
IK
VCC = 4.75 V , II = –18 mA –1.2 V
IOH = –15 mA 2.4 3.3
VOHV
CC
= 4.75
V
IOH = –24 mA 2 3.1
V
V
OL
VCC = 4.75 V , IOL = 48 mA 0.35 0.5 V
I
OZH
VCC = 5.25 V , VO = 2.4 V 20 µA
I
OZL
VCC = 5.25 V , VO = 0.4 V –20 µA
I
I
VCC = 5.25 V , VI = 5.5 V 0.1 mA
I
IH
VCC = 5.25 V , VI = 2.7 V 20 µA
I
IL
VCC = 5.25 V , VI = 0.4 V –0.2 mA
I
OS
‡
VCC = 5.25 V , VO = 0 –75 –250 mA
I
CC
VCC = 5.25 V , Outputs open 80 115 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics (see Figure 1)
FROM TO
VCC = MIN to MAX§,
TA = MIN to MAX
§
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
SN74ALS29823
UNIT
MIN MAX
t
PLH
2 10
t
PHL
CLK
A
ny
Q
C
L
= 50 p
F
2 10
ns
t
PLH
16
t
PHL
CLK
A
ny
Q
C
L
=
300 pF
16
ns
t
PHL
CLR Any Q CL = 50 pF 12 ns
t
PZH
14
t
PZL
OE
A
ny
Q
C
L
= 50 p
F
14
ns
t
PZH
20
t
PZL
OE
A
ny
Q
C
L
=
300 pF
23
ns
t
PHZ
14
t
PLZ
OE
A
ny
Q
C
L
=
50 pF
12
ns
t
PHZ
p
9
t
PLZ
OE
A
ny
Q
C
L
= 5 p
F
9
ns
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Page 6
SN54ALS29823, SN74ALS29823
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT
R1
1 kΩ
All Diodes
1N916 or 1N3064
From Output
Under Test
Test Point
S2
C
L
(see Note A)
RL = 180 Ω
1.5 V
1.5 V
1.5 V
3 V
3 V
0
0
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
Data Input
1.5 V
1.5 V
3 V
3 V
0
0
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V
1.5 V
t
PHL
t
PLH
t
PLH
t
PHL
Out-of-Phase
Output
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHZ
t
PLZ
0.5 V
t
PZL
t
PZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0
Output
Control
Waveform 1
(see Note B)
Waveform 2
(see Note B)
≈ 0
V
OH
V
OL
≈ 1.5 V
0.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
V
CC
S1
SWITCH POSITION TABLE
TEST S1 S2
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Open
Closed
Closed
≈ 4.5 V
≈ 1.5 V
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
Page 7
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Copyright 1998, Texas Instruments Incorporated
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