Datasheet SN74ALS233BDW, SN74ALS233BDWR, SN74ALS233BFN, SN74ALS233BN Datasheet (Texas Instruments)

SN74ALS233B

16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Independent Asychronous Inputs and
Outputs

D

16 Words by 5 Bits

D

Data Rates From up to 40 MHz

D

Fall-Through Time 14 ns Typ

D

3-State Outputs

D

Package Options Include Plastic
Small-Outline Package (DW), Plastic Chip
Carriers (FN), and Standard Plastic 300-mil
DIPs (N)

description

This 80-bit memory uses advanced low-power
Schottky technology and features high speed and
a fast fall-through time. It is organized as 16 words
by 5 bits.

A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. This FIFO is designed to
process data at rates up to 40 MHz in a bit-parallel
format, word by word.

Data is written into memory on a low-to-high
transition at the load clock (LDCK) input and is
read out on a low-to-high transition at the unload
clock (UNCK) input. The memory is full when the
number of words clocked in exceeds by 16 the
number of words clocked out. When the memory
is full, LDCK signals have no effect. When the
memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the FULL

, EMPTY , FULL–1, and EMPTY+1 output flags. The FULL
output is low when the memory is full and high when it is not full. The FULL–1 output is low when the memory
contains 15 data words. The EMPTY

output is low when the memory is empty and high when it is not empty.

The EMPTY+1

output is low when one word remains in memory.

A low level on the reset (RST

) input resets the internal stack control pointers and also sets EMPTY low and sets

FULL

, FULL–1, and EMPTY+1 high. The Q outputs are not reset to any specific logic level. The first low-to-high

transition on LDCK, after either a RST

pulse or from an empty condition, causes EMPTY to go high and the data
to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs
are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input
is low. OE does not af fect the output flags. Cascading is easily accomplished in the word-width direction but is
not possible in the word-depth direction.

The SN74ALS233B is characterized for operation from 0°C to 70°C.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10

OE

FULL–1

FULL

LDCK

D0
D1
D2
D3
D4

GND

V

CC

EMPTY+1
UNCK
EMPTY
Q0
Q1
Q2
Q3
Q4
RST

DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

UNCK
EMPTY
Q0
Q1
Q2

LDCK

D0
D1
D2
D3

FN PACKAGE

(TOP VIEW)

FULL

FULL–1

OE

Q4

Q3

EMPTY+1

D4

GND

RST

V

CC

20
19
18
17
16
15
14
13
12
11

18
17
16
15
14

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74ALS233B
16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

CT = 0

11

EN4

1

OE

2D

5

D0

17

(CT = 0) G3

Q0

16

6

D1

Q1

15

7

D2

Q2

14

8

D3

Q3

13

9

D4

Q4

12

18

UNCK

19

CT = 1

2

CT = 15

3

(CT = 16) G1

4

LDCK

FIFO 16 × 5

(ALS233B)

CTR

RST

FULL
FULL–1
EMPTY+1

EMPTY

3–

1

(+/C2)

4

†

This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. The symbol is functionally accurate but does
not show the details of implementation; for these, see the logic diagram. The symbol represents the memory as if it were controlled by a single
counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0.

SN74ALS233B

16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1A, 3D

5

D0

6

D1

7

D2

8

D3

9

D4

Q0

16

2A

Q1

15

Q2

14

Q3

13

Q4

12

C3

EN

3

2

19

17

FULL

FULL–1

EMPTY+1

EMPTY

RAM 16 × 5

1A

16

2A

16

1

16

1

16

7
8

9
10
11
12
13
14
15
16

1

2

3

4

5

6

+

CT = 1

COMP

P = Q

P = Q + 2
P = Q – 2

P

Q

1616

S

R

7

8

9
10
11
12
13
14
15
16

1

2

3

4

5

6

+

CT = 1

18

UNCK

C1
1D

S

R

4

LDCK

C1

1D

11

RST

1

OE

Ring

Counter

CTR

DIV 16

Write

Address

Read

Address

16

Ring

Counter

CTR

DIV 16

SN74ALS233B
16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing diagram

Invalid

RST

LDCK

D0–D4

UNCK

Q0–Q4

EMPTY

EMPTY+1

FULL

FULL–1

W1 W2 W3 W1 W2 W3 W14 W15 W16

Don’t Care

Word 1 Word 2 Word 3 Invalid Word 1 Word 2 Word 3 Word 4

Initialize
Pointers

Load

W1

Unload

W2

Empty Empty+1 Full–1 Full

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 1): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FN package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length

of zero.

SN74ALS233B

16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 V

V

IL

Low-level input voltage 0.8 V

p

Q outputs –1.6

IOHHigh-level output current

Status flags –0.4

mA

p

Q outputs 24

IOLLow-level output current

Status flags 8

mA

T

A

Operating free-air temperature 0 70 °C

NOTE 2: T o ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs.

Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse duration limits can cause a false clock
or improper operation of the internal read and write pointers.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 V

Q outputs VCC = 4.5 V, IOH = –2.6 mA 2.4 3.2

V

OH

Status flags VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2

V

p

IOL = 12 mA 0.25 0.4

Q outputs

V

CC

= 4.5

V

IOL = 24 mA 0.35 0.5

V

OL

IOL = 4 mA 0.25 0.4

V

Status flags

V

CC

=

4.5 V

IOL = 8 mA 0.35 0.5

I

OZH

VCC = 5.5 V, VO = 2.7 V 20 µA

I

OZL

VCC = 5.5 V, VO = 0.4 V –20 µA

I

I

VCC = 5.5 V, VI = 7 V 0.1 mA

I

IH

VCC = 5.5 V, VI = 2.7 V 20 µA

I

IL

VCC = 5.5 V, VI = 0.4 V –0.2 mA

I

O

‡

VCC = 5.5 V, VO = 2.25 V –30 –112 mA

I

CC

VCC = 5.5 V 88 133 mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.

SN74ALS233B
16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)

MIN NOM MAX UNIT

LDCK 40

f

clock

Clock frequenc

y

UNCK

40

MH

z

RST low 18
LDCK low 15

t

w

Pulse duration

LDCK high 10

ns
UNCK low 15
UNCK high 10
Data before LDCK↑ 8

t

su

Setup time

RST (inactive) before LDCK↑ 5

ns
LDCK (inactive) before RST↑ 5

t

h

Hold time Data after LDCK↑ 5 ns

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN MAX UNIT

f

max

LDCK, UNCK 40 MHz

LDCK↑

6 32

t

pd

UNCK↑

Any Q

6 30

ns

t

PLH

LDCK↑

EMPTY

5 25 ns

UNCK↑

6 27

t

PHL

RST↓

EMPTY

5 25

ns

LDCK↑

7 34

t

pd

UNCK↑

EMPTY+1

7 34

ns

t

PLH

RST↓ EMPTY+1 8 31 ns

LDCK↑

9 33

t

pd

UNCK↑

FULL–1

8 32

ns

t

PLH

RST↓ FULL–1 11 32 ns

t

PHL

LDCK↑ FULL 6 27 ns
UNCK↑

5 25

t

PLH

RST↓

FULL

9 30

ns

t

en

OE↑ Q 2 15 ns

t

dis

OE↓ Q 1 15 ns

SN74ALS233B

16 × 5 ASYNCHRONOUS FIRST -IN, FIRST-OUT MEMORY

SCAS253B – MARCH 1990 – REVISED APRIL 1998

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

PHZ

t

PLZ

t

PHL

t

PLH

0.3 V

t

PZL

t

PZH

t

PLH

t

PHL

LOAD CIRCUIT FOR 3-STATE OUTPUTS

From Output

Under Test

Test Point

R1 = 500 Ω

S1

CL = 50 pF

(see Note A)

7 V

Open

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

VOLTAGE WAVEFORMS

PULSE DURATION

Input

(see Note C)

Out-of-Phase

Output

1.3 V

1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

V

OL

V

OH

V

OH

V

OL

Output

Control

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

0 V

V

OH

V

OL

3.5 V

In-Phase

Output

0.3 V

1.3 V

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2 = 500 Ω

t

w

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PLH

t

PHL

Open
Closed
Open
Closed
Open
Open

PARAMETER S1

t

en

t

dis

t

pd

Figure 1. Load Circuit and Voltage Waveforms

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Copyright  1999, Texas Instruments Incorporated