Datasheet SN74ALS2240DW, SN74ALS2240N Datasheet (Texas Instruments)

SN74ALS2240

OCTAL BUFFER AND LINE DRIVER/MOS DRIVER

WITH 3-STATE OUTPUTS

SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997

D

Bidirectional Quadruple-Bus Transceivers
for Driving MOS Devices

D

I/O Ports Have 25-Ω Series Resistors, So
No External Resistors Are Required

D

Package Options Include Plastic
Small-Outline (DW) Package and Standard
Plastic (N) 300-mil DIPs

description

This octal buffer and line driver/MOS driver is
designed to drive the capacitive inputs of MOS
devices and to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. This device features high fan-out
and improved fan-in.

The SN74ALS2240 is characterized for operation
from 0°C to 70°C.

FUNCTION TABLE

(each buffer)

INPUTS

OE A

L H L
L LH

HXZ

OUTPUT

Y

DW OR N PACKAGE

(TOP VIEW)

1

1OE

2

1A1

3

2Y4

4

1A2

5

2Y3

6

1A3

7

2Y2

8

1A4

9

2Y1

GND

10

20
19
18
17
16
15
14
13
12
11

V

CC

2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1

1OE

2

1A1

4

1A2

6

1A3

8

1A4

19

2OE

11

2A1

13

2A2

15

2A3

17

2A4

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EN

EN

18
16
14
12

1Y1
1Y2
1Y3
1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS

SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997

logic diagram (positive logic)

†

1

1OE

1A1

1A2

1A3

1A4

2OE

2A1

2A2

2

4

6

8

19

11

13

18

16

14

12

1Y1

1Y2

1Y3

1Y4

9

2Y1

7

2Y2

15

2A3

17 3

2A4

†

All output resistors are 25 Ω.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
Input voltage, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

: All inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

5

2Y3

2Y4

‡

I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T
Package thermal impedance, θ

–65°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

JA

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

(see Note 1): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51, except for through hole packages, which use a trace length

of zero.

2

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VOLV

V

V

A

Y

ns

SN74ALS2240

OCTAL BUFFER AND LINE DRIVER/MOS DRIVER

WITH 3-STATE OUTPUTS

SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997

recommended operating conditions

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

T

A

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.

Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Operating free-air temperature 0 70 °C

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

I

OZH

I

OZL

I

I

I

IH

I

IL

I

O

I

OH

I

OL

I

CC

‡

VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 V

= 4.5

CC

VCC = 5.5 V, VO = 2.7 V 20 µA
VCC = 5.5 V, VO = 0.4 V –20 µA
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 mA
VCC = 4.5 V, –15 mA
VCC = 4.5 V, 15 mA

VCC = 5.5 V

IOL = 1 mA 0.15 0.5
IOL = 12 mA 0.35 0.8

Outputs high 6 11
Outputs low 13 23
Outputs disabled 12 20

mA

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

FROM

(INPUT)

OE
OE
OE
OE

TO

(OUTPUT)

Y 5 17 ns
Y 7 20 ns
Y 2 10 ns
Y 4 15 ns

R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX

UNIT

§

MIN MAX

2 10
2 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ALS2240
OCTAL BUFFER AND LINE DRIVER/MOS DRIVER
WITH 3-STATE OUTPUTS

SDAS268A – DECEMBER 1994 – REVISED NOVEMBER 1997

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

V

CC

From Output

Under Test

(see Note A)

C

L

Test
Point

R

L

From Output

Under Test

C

(see Note A)

L

R

L

Test
Point

From Output

Under Test

(see Note A)

7 V

RL = R1 = R2

S1

R1

C

L

Test
Point

R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

t

PZL

t

PZH

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

1.3 V

t

PHZ

1.3 V

1.3 V

t

1.3 V1.3 V

1.3 V1.3 V

FOR OPEN-COLLECTOR OUTPUTS

h

t

PLZ

LOAD CIRCUIT

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

[

3.5 V

V

OL

0.3 V

V

OH

0.3 V

[

0 V

High-Level

Low-Level

Out-of-Phase

(see Note C)

Pulse

Pulse

Input

In-Phase

Output

Output

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

t

PLH

t

PHL

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V1.3 V

t

PHL

t

PLH

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

V

V

V

V

OH

OL

OH

OL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

4

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Copyright  1998, Texas Instruments Incorporated