Datasheet SN74AHCT16374DGGR, SN74AHCT16374DGVR, SN74AHCT16374DL, SN74AHCT16374DLR Datasheet (Texas Instruments)
Page 1
SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
D
Members of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHCT16374 devices are 16-bit
edge-triggered D-type flip-flops with 3-state
outputs designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
SN54AHCT16374 . . . WD PACKAGE
SN74AHCT16374 . . . DGG, DGV, OR DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE
does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AHCT16374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Page 2
SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
CLK D
OE
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
2EN
1D
2D
C1
C2
11
12
13
14
16
17
19
20
22
23
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
1OE
1CLK
2OE
2CLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
2
1OE
1CLK
1D1
1
48
47
C1
1D
To Seven Other Channels
1Q1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2OE
2CLK
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
Page 3
UNIT
SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, I
Output clamp current, I
(see Note 1) –0.5 V to V
O
(V
IK
I
OK
Continuous output current, I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHCT16374 SN74AHCT16374
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 20 20 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current –8 –8 mA
Low-level output current 8 8 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54AHCT16374, SN74AHCT16374
PARAMETER
TEST CONDITIONS
V
UNIT
V
4.5 V
V
V
4.5 V
V
UNIT
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
OH
OL
I
I
I
OZ
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VO = VCC or GND,
VI = VIH or V
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,
†
Other inputs at VCC or GND
VI = VCC or GND 5 V 2.5 10 10 pF
VO = VCC or GND 5 V 3.5 pF
IL
5.5 V ±0.25 ±2.5 ±2.5
5.5 V 1.35 1.5 1.5 mA
TA = 25°C SN54AHCT16374 SN74AHCT16374
MIN TYP MAX MIN MAX MIN MAX
4.4 4.5 4.4 4.4
3.94 3.8 3.8
0.1 0.1 0.1
0.36 0.44 0.44
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHCT16374 SN74AHCT16374
MIN MAX MIN MAX MIN MAX
t
Pulse duration, CLK high or low 6.5 6.5 6.5 ns
w
t
Setup time, data before CLK↑
su
t
Hold time, data after CLK↑ 2.5 2.5 2.5 ns
h
2.5 2.5 2.5 ns
= 5 V ± 0.5 V
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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Page 5
PARAMETER
UNIT
f
MH
CLKQC
15 pF
ns
OE
Q
C
pF
ns
OE
Q
C
15 pF
ns
CLKQC
50 pF
ns
OE
Q
C
pF
ns
OE
Q
C
pF
ns
PARAMETER
UNIT
SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 15 pF 90* 140* 80* 110
CL = 50 pF 85 130 75 75
p
=
L
p
= 15
L
p
=
L
p
=
L
p
= 50
L
p
= 50
L
CL = 50 pF 1** 1 ns
TA = 25°C SN54AHCT16374 SN74AHCT16374
MIN TYP MAX MIN MAX MIN MAX
6.5* 9.4* 1* 10.5* 1 10.5
6.5* 9.4* 1* 10.5* 1 10.5
6.5* 9.5* 1* 10.5* 1 10.5
6.5* 9.5* 1* 10.5* 1 10.5
6.2* 10.2* 1* 11* 1 11
6.2* 10.2* 1* 11* 1 11
7.3 10.4 1 11.5 1 11.5
7.1 10.4 1 11.5 1 11.5
6.2 10.5 1 11.5 1 11.5
5.1 10.5 1 11.5 1 11.5
7.1 11.2 1 12 1 12
7.9 11.2 1 12 1 12
z
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2 V
Low-level dynamic input voltage 0.8 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 27 pF
pd
= 5 V, C
CC
CC
PARAMETER TEST CONDITIONS TYP UNIT
= 50 pF, TA = 25°C (see Note 4)
L
OL
OL
OH
= 5 V, TA = 25°C
SN74AHCT16374
MIN TYP MAX
0.36 0.8 V
–0.1 –0.8 V
4.7 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
SN54AHCT16374, SN74AHCT16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS337I – MARCH 1996 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
V
CC
GND
Open
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3-STATE AND OPEN-DRAIN OUTPUTS
CC
CC
LOAD CIRCUIT FOR
3 V
0 V
3 V
0 V
t
PHL
V
t
PLH
CC
CC
OH
V
OL
V
OH
V
OL
50% V
50% V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
1.5 V
t
CC
CC
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
6
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Page 7
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performed, except those mandated by government requirements.
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