Page 1
D
Members of the Texas Instruments
Widebus+
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Released as DSCC SMD 5962-9557601NXD
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
D
Typical V
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14 × 14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package
(Output Ground Bounce)
OLP
†
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
V
CC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2A11
2A12
2A13
2A14
GND
’ABTH32501 ...PZ PACKAGE
2A15
2A16
2A17
2A18
(TOP VIEW)
V
2OEBA
2LEBA
2CLKBA
CC
2CLKAB
2LEAB
2OEAB
2B18
2B17
2B16
2B15
2B14
GND
2B13
2B12
767778798081828384858687888990919293949596979899100
494847464544434241403938373635343332313029282726
50
2B11
2B10
75
2B9
74
GND
73
2B8
72
2B7
71
2B6
70
2B5
69
GND
68
2B4
67
2B3
66
2B2
65
2B1
64
V
63
CC
1B1
62
1B2
61
1B3
60
1B4
59
GND
58
1B5
57
1B6
56
1B7
55
1B8
54
GND
53
1B9
52
1B10
51
GND
1A11
1A12
1A13
1A14
1A15
1A16
1A17
1A18
†
The HS package is not production released.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1OEBA
CC
1LEBA
1CLKBAV1CLKAB
1LEAB
1B18
1B17
1OEAB
1B16
1B15
GND
1B14
1B11
1B13
1B12
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
2A13
2A12
2A11
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
V
CC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
1A11
1A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SN54ABTH32501 . . . HS PACKAGE
GND
2A14
2A16
2A15
97
98
99
100
34
33
32
31
2A17
2A18
95
96
36
35
(TOP VIEW)
2CLKBA
2LEABA
2OEBA
92
93
94
39
38
37
91
CC
V
40
2OEAB
2LEAB
2CLKAB
88
89
90
43
42
41
2B17
2B18
86
87
45
44
†
2B16
2B15
84
85
47
46
2B14
GND
82
83
49
48
2B13
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
2B12
2B11
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
V
CC
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
1B11
1B12
1B13
CC
GND
1A13
1A14
1A15
1A16
1A17
1A18
1OEBA
†
For HS package availability, please contact the factory or your local TI Field Sales Of fice.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
1LEBA
1CLKBA
1LEAB
1OEAB
1CLKAB
1B18
1B17
1B16
1B15
GND
1B14
Page 3
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
description
These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low , the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar
to that of A to B, but uses OEBA
Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is
active low).
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32501 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32501 is characterized for operation from –40°C to 85°C.
, LEBA, and CLKBA.
FUNCTION TABLE
INPUTS
OEAB LEAB CLKAB A
L X X X Z
H HXLL
H HXHH
H L ↑ LL
H L ↑ HH
H LHXB
H L L X B
†
A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA
‡
Output level before the indicated steady-state input
conditions were established
§
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
, LEBA, and CLKBA.
†
OUTPUT
B
‡
0
§
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
logic diagram (positive logic)
1OEAB
1CLKBA
1LEBA
1OEBA
1CLKAB
1LEAB
1A1
2OEAB
2CLKBA
2LEBA
2OEBA
2CLKAB
2LEAB
2A1
41
37
36
35
39
40
14
85
89
90
91
87
86
12
CLK
LE
D
To 17 Other Channels
CLK
LE
D
CLK
LE
62
1B1
D
64
2B1
Pin numbers shown are for the PZ package.
4
CLK
LE
D
To 17 Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
UNIT
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH32501 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): PZ package 50°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABTH32501 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABTH32501 SN74ABTH32501
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
SN54ABTH32501, SN74ABTH32501
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
A
V
V
V
GND
I
A or B ports
V
V
A
V
I
V
CC
GND
UNIT
twPulse duration
ns
tsuSetup time
ns
thHold time
ns
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH32501 SN74ABTH32501
MIN TYP†MAX MIN TYP†MAX
V
IK
OH
V
hys
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1
I
I(hold)
I
OZPU
I
OZPD
I
off
I
CEX
I
O
I
CC
∆I
C
C
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
This parameter is specified by characterization.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20
Control inputs
A or B ports
p
‡
‡
§
¶
CC
Control inputs VI = 2.5 V or 0.5 V 3.5 3.5 pF
i
A or B ports VO = 2.5 V or 0.5 V 11.5 11.5 pF
io
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
= 4.5
CC
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V,
OE or OE
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V,
OE or OE
VCC = 0, VI or VO ≤ 4.5 V ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –100 –180 mA
VCC = 5.5 V, IO = 0,
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
=
= X
= X
or
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55
100 100 mV
=
or
I
CC
VI = 0.8 V 100 100
VI = 2 V –100 –100
Outputs high 6 6
Outputs low 90 90 mA
Outputs disabled 6 6
±5
±50
±50 ±50 µA
±50 ±50 µA
1 1 mA
µ
µ
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABTH32501 SN74ABTH32501
MIN MAX MIN MAX
6
f
clock
Clock frequency 0 150 0 150 MHz
LE high 3.5 3.3
CLK high or low 3.5 3.3
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A or B before CLK↑ 4.3 3.5
A or B before LE↓ 2.5 1.6
A or B after CLK↑ 0.2 0
A or B after LE↓ 1.8 1.6
Page 7
PARAMETER
UNIT
A or B
B or A
ns
LEAB or LEBA
A or B
ns
CLKAB or CLKBA
A or B
ns
OEAB
OEBA
A or B
ns
OEAB
OEBA
A or B
ns
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
†
All typical values are at VCC = 5 V, TA = 25°C.
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM TO
(INPUT) (OUTPUT)
or
or
SN54ABTH32501 SN74ABTH32501
MIN TYP†MAX MIN TYP†MAX
150 150 MHz
0.5 2.9 5.2 1.3 2.9 4.8
0.5 2.7 5.8 1.4 2.7 5.4
0.7 3.4 5.7 1.6 3.4 5.3
0.7 3.6 5.9 1.9 3.6 5.5
0.5 3.2 5.7 1.5 3.2 5.3
0.7 3.3 5.8 1.7 3.3 5.4
0.5 3.2 6.2 1.2 3.2 5.6
0.5 3.6 6.6 1.5 3.6 6
0.7 3.6 7 1.8 3.6 5.9
0.7 3.5 6.1 1.7 3.5 5.6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
GND
OH
OL
OH
OL
Open
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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