Datasheet SN74ABT8952DL, SN74ABT8952DLR, SN74ABT8952DW, SN74ABT8952DWR Datasheet (Texas Instruments)

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SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

Members of the Texas Instruments

SCOPE

Compatible With the IEEE Standard

 Family of Testability Products

1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture

Functionally Equivalent to ’BCT2952 and ’ABT2952 in the Normal-Function Mode

SCOPE

IEEE Standard 1149.1-1990 Required

 Instruction Set

Instructions, Optional INTEST, CLAMP, and HIGHZ

Parallel-Signature Analysis at Inputs With Masking Option

Pseudo-Random Pattern Generation From Outputs

Sample Inputs/Toggle Outputs

Binary Count From Outputs

Even-Parity Opcodes

Two Boundary-Scan Cells Per I/O for Greater Flexibility

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

description

The ’ABT8952 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPE  testability integra- ted-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

SN54ABT8952 . . . JT PACKAGE

SN74ABT8952 . . . DL OR DW PACKAGE

CLKAB

CLKENAB

OEAB

SN54ABT8952 . . . FK PACKAGE

OEBA

CLKENBA

CLKBA CLKAB

CLKENAB

OEAB

A1 A2 A3

GND

A4 A5 A6 A7

A8 TDO TMS

5 6 7 8 9 10 11

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(TOP VIEW)

B1B2B3

321

13 14

GND

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VB5B6

28 27 26

15 16 17 18

A4A5A6

CLKBA CLKENBA OEBA B1 B2 B3 B4 V

B5 B6 B7 B8 TDI TCK

25 24 23 22 21 20 19

B7 B8 TDI TCK TMS TDO A8

In the normal mode, these devices are functionally equivalent to the ’BCT2952 and ’ABT2952 octal registered bus transceivers. The test circuitry can be activated by the T AP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the T AP in normal mode does not affect the functional operation of the SCOPE octal registered bus transceivers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ΙΙB are trademarks of Texas Instruments Incorporated.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

description (continued)

Data flow in each direction is controlled by clock (CLKAB and CLKBA), clock-enable (CLKENAB and CLKENBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, A-bus data is stored in the associated registers on the low-to-high transition of CLKAB, provided that CLKENAB CLKENAB is high or CLKAB remains at a static low or high level, the register contents are not changed. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B, but uses CLKBA, CLKENBA, and OEBA.

In the test mode, the normal operation of the SCOPE registered bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8952 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT8952 is characterized for operation from –40°C to 85°C.

is low. Otherwise, if

FUNCTION TABLE

(normal mode, each register)

INPUTS

OEAB CLKENAB CLKAB A

L L ↑ L L L L ↑ HH L HXXB L XLXB

H X X X Z

†

A-to-B data flow is shown; B-to-A data flow is similar but uses OEBA

, CLKENBA, and CLKBA.

†

OUTPUT

0 0

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functional block diagram

OEBA

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

Boundary-Scan Register

CLKENBA

CLKBA

OEAB

CLKENAB

CLKAB

MUX

1 1

MUX G1 1 1

One of Eight Channels

TDI

TMS

TAP

TCK

Pin numbers shown are for the DL, DW, and JT packages.

Controller

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Bypass Register

Boundary-Control

Instruction Register

TDO

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

Terminal Functions

TERMINAL

NAME

A1–A8 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1–B8 Normal-function B-bus I/O ports. See function table for normal-mode logic.

CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.

CLKENAB, CLKENBA Normal-function clock-enable inputs. See function table for normal-mode logic.

GND Ground

OEAB, OEBA Normal-function output-enable inputs. See function table for normal-mode logic.

TCK

TDI

TDO

TMS V

T est clock. One of four pins required by IEEE Standard 1149.1-1990. T est operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

Test data input. One of four pins required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

T est data output. One of four pins required by IEEE Standard 1 149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register.

T est mode select. One of four pins required by IEEE Standard 1 149.1-1990. TMS directs the device through its T AP controller states. An internal pullup forces TMS to a high level if left unconnected.

Supply voltage

DESCRIPTION

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SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard 1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The T AP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the T AP controller, and the test registers. As illustrated, the device contains an 8-bit instruction register and three test-data registers: a 38-bit boundary-scan register, an 11-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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Update-IR

TMS = LTMS = H

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

state diagram description

The T AP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state as a state the T AP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.

For the ’ABT8952, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. Each bit in the boundary-scan register is reset to logic 0 except bits 37–36, which are reset to logic 1. The boundary-control register is reset to the binary value 00000000010, which selects the PSA test operation with no input masking.

Run-Test/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.

The test operations selected by the boundary-control register are performed while the T AP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

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SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the ’ABT8952, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

T able 3 lists the instructions supported by the ’ABT8952. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated, and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.

Bit 7 Parity (MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

TDOTDI

Figure 2. Instruction Register Order of Scan

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SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

data register description

boundary-scan register

The boundary-scan register (BSR) is 38 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output data). The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, the value of each BSC is reset to logic 0 except BSCs 37–36, which are reset to logic 1.

The BSR order of scan is from TDI through bits 37–0 to TDO. T able 1 shows the BSR bits and their associated device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

37 OEAB 31 A8-I 23 A8-O 15 B8-I 7 B8-O 36 OEBA 30 A7-I 22 A7-O 14 B7-I 6 B7-O 35 CLKAB 29 A6-I 21 A6-O 13 B6-I 5 B6-O 34 CLKBA 28 A5-I 20 A5-O 12 B5-I 4 B5-O 33 CLKENAB 27 A4-I 19 A4-O 11 B4-I 3 B4-O 32 CLKENBA 26 A3-I 18 A3-O 10 B3-I 2 B3-O –– –– 25 A2-I 17 A2-O 9 B2-I 1 B2-O –– –– 24 A1-I 16 A1-O 8 B1-I 0 B1-O

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

boundary-control register

The boundary-control register (BCR) is 1 1 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA with input masking, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 00000000010, which selects the PSA test operation with no input masking.

The BCR order of scan is from TDI through bits 10–0 to TDO. T able 2 shows the BCR bits and their associated test control signals.

Table 2. Boundary-Control Register Configuration

BCR BIT

NUMBER

10 MASK8 6 MASK4 2 OPCODE2

9 MASK7 5 MASK3 1 OPCODE1 8 MASK6 4 MASK2 0 OPCODE0 7 MASK5 3 MASK1 –– ––

TEST

CONTROL

SIGNAL

BCR BIT

NUMBER

TEST

CONTROL

SIGNAL

BCR BIT

NUMBER

TEST

CONTROL

SIGNAL

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation.

During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 3.

Bit 0

TDOTDI

Figure 3. Bypass Register Order of Scan

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SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction.

Table 3. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

00000000 EXTEST/INTEST Boundary scan Boundary scan Test 10000001 BYPASS 10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal 0000001 1 INTEST/EXTEST Boundary scan Boundary scan Test 10000100 BYPASS 00000101 BYPASS 00000110 HIGHZ Control boundary to high impedance Bypass Modified test 100001 11 CLAMP Control boundary to 1/0 Bypass Test 10001000 BYPASS 00001001 RUNT Boundary run test Bypass Test 00001010 READBN Boundary read Boundary scan Normal 1000101 1 READBT Boundary read Boundary scan Test 00001 100 CELLTST Boundary self test Boundary scan Normal 10001 101 TOPHIP Boundary toggle outputs Bypass Test 10001 110 SCANCN Boundary-control register scan Boundary control Normal

00001 111 SCANCT Boundary-control register scan Boundary control Test All others BYP ASS Bypass scan Bypass Normal

†

Bit 7 is used to maintain even parity in the 8-bit instruction.

‡

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABT8952.

†

SCOPE OPCODE DESCRIPTION

‡

‡ ‡

‡

SELECTED DATA

Bypass scan Bypass Normal

Bypass scan Bypass Normal Bypass scan Bypass Normal

Bypass scan Bypass Normal

MODE

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into the output BSCs is applied to the device output pins. The device operates in the test mode.

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the normal mode.

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output pins. The device operates in the test mode.

boundary run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way , the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of TCK in Run-T est/Idle, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary run test operation to specify which test operation is to be executed.

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SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

boundary-control register opcode description

The BCR opcodes are decoded from BCR bits 2–0 as shown in T able 4. The selected test operation is performed while the RUNT instruction is executed in the Run-T est/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

X00 Sample inputs/toggle outputs (TOPSIP) X01 Pseudo-random pattern generation/16-bit mode (PRPG) X10 Parallel-signature analysis/16-bit mode (PSA)

011 Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG) 111 Simultaneous PSA and binary count up/8-bit mode (PSA/COUNT)

In general, while the control input BSCs (bits 37–32) are not included in the sample, toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 37–36 of the BSR) do control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are valid only when the device is operating in one direction of data flow (that is, OEAB ≠OEBA). Otherwise, the bypass instruction is operated.

DESCRIPTION

PSA input masking

Bits 10–3 of the BCR specify device input pins to be masked from PSA operations. Bit 10 selects masking for device input pin A8 during A-to-B data flow or for device input pin B8 during B-to-A data flow. Bit 3 selects masking for device input pins A1 or B1 during A-to-B or B-to-A data flow, respectively. Bits intermediate to 10 and 3 mask corresponding device input pins in order from most significant to least significant, as indicated in Table 3. When the mask bit that corresponds to a particular device input has a logic 1 value, the device input pin is masked from any PSA operation, i.e., that the state of the device input pin is ignored and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not masked from the PSA operation.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK.

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Figures 4 and 5 illustrate the 16-bit linear-feedback shift-register algorithms through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns.

A8-I

A7-I A6-I A5-I A4-I A3-I A2-I A1-I

B8-O

B7-O B6-O B5-O B4-O B3-O B2-O B1-O

Figure 4. 16-Bit PRPG Configuration (OEAB = 0, OEBA = 1)

B8-I

A8-O

B7-I B6-I B5-I B4-I B3-I B2-I B1-I

A7-O A6-O A5-O A4-O A3-O A2-O A1-O

Figure 5. 16-Bit PRPG Configuration (OEAB=1, OEBA = 0)

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SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

parallel-signature analysis (PSA)

Data appearing at the selected device input pins is compressed into a 16-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 6 and 7 illustrate the 16-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

MASKX

A8-I

B8-O

A7-I A6-I A5-I A4-I A3-I A2-I A1-I

B7-O B6-O B5-O B4-O B3-O B2-O B1-O

Figure 6. 16-Bit PSA Configuration (OEAB = 0, OEBA = 1)

B8-I

B7-I B6-I B5-I B4-I B3-I B2-I B1-I

A8-O

A7-O A6-O A5-O A4-O A3-O A2-O A1-O

Figure 7. 16-Bit PSA Configuration (OEAB = 1, OEBA = 0)

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SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. Figures 8 and 9 illustrate the 8-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns.

A8-I

MASKX

A7-I A6-I A5-I A4-I A3-I A2-I A1-I

MASKX

B8-O

B7-O B6-O B5-O B4-O B3-O B2-O B1-O

Figure 8. 8-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)

B8-I

A8-O

B7-I B6-I B5-I B4-I B3-I B2-I B1-I

A7-O A6-O A5-O A4-O A3-O A2-O A1-O

Figure 9. 8-Bit PSA/PRPG Configuration (OEAB = 1, OEBA = 0)

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SCAN TEST DEVICES WITH

OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input pins is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. In addition, the shift-register elements of the opposite output BSCs count carries out of the selected output BSCs extending the count to 16 bits. Figures 10 and 11 illustrate the 8-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

A8-I

MASKX

A7-I A6-I A5-I A4-I A3-I A2-I A1-I

MASKX

MSB LSB

B8-O

B7-O B6-O B5-O B4-O B3-O B2-O B1-O

Figure 10. 8-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 1)

B8-I

MSB LSB

A8-O

B7-I B6-I B5-I B4-I B3-I B2-I B1-I

A7-O A6-O A5-O A4-O A3-O A2-O A1-O

Figure 11. 8-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 0)

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

timing description

All test operations of the ’ABT8952 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK. The T AP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 12. In this example, the TAP controller begins in the T est-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used to output serial data. The T AP controller is then returned to the Test-Logic-Reset state. Table 5 details the operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

1 Test-Logic-Reset 2 Run-Test/Idle

3 Select-DR-Scan 4 Select-IR-Scan

5 Capture-IR

6 Shift-IR

7–13 Shift-IR

14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. 16 Select-DR-Scan

17 Capture-DR

18 Shift-DR

19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR In general, the selected data register is updated with the new data on the falling edge of TCK. 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset Test operation completed

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state.

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

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Page 19

UNIT

TCK

TMS

TDO

SN54ABT8952, SN74ABT8952

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OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TDI

TAP

Controller

State

Run-Test/Idle

Test-Logic-Reset

Select-DR-Scan

Capture-IR

Select-IR-Scan

Shift-IR

3-State (TDO) or Don’t Care (TDI)

Exit1-IR

Update-IR

Capture-DR

Select-DR-Scan

Shift-DR

Exit1-DR

Update-DR

Select-IR-Scan

Select-DR-Scan

Figure 12. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (I/O ports) (see Note 1) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT8952 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT8952 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I Output clamp current, I

Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DL package 0.7 W. . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the

Book

, literature number SCBD002.

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 1.7 W. . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

application note in the

ABT Advanced BiCMOS T echnology Data

Test-Logic-Reset

†

recommended operating conditions (see Note 3)

SN54ABT8952 SN74ABT8952

MIN MAX MIN MAX

V V V V I

∆t/∆v Input transition rise or fall rate 10 10 ns/V T

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Supply voltage 4.5 5.5 4.5 5.5 V

High-level input voltage 2 2 V

Low-level input voltage 0.8 0.8 V

Input voltage 0 V

High-level output current –24 –32 mA Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

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0 V

Page 20

SN54ABT8952, SN74ABT8952

PARAMETER

TEST CONDITIONS

UNIT

4.5 V

GND

orts

∆I

1.5

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

TA = 25°C SN54ABT8952 SN74ABT8952

MIN TYP†MAX MIN MAX MIN MAX

OZH

OZL

off

OZPU

OZPD

CEX

*On products compliant to MIL-PRF-38535, this parameter does not apply. †

All typical values are at VCC = 5 V.

‡

The parameters I

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3

= 4.5

VCC = 5.5 V,

VCC = 5.5 V, VI = V VCC = 5.5 V, VI = GND TDI, TMS –40 –160 –40 –160 –40 –160 µA

‡

VCC = 5.5 V, VO = 2.7 V 50 50 50 µA

‡

VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA VCC = 0 to 2 V, VO = 0.5 V or 2.7 V ±50 ±50 ±50 µA VCC = 2 V to 0, VO = 0.5 V or 2.7 V ±50 ±50 ±50 µA VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

= 5.5 V, IO = 0, VI = VCC or GND

= 5.5 V, One input at 3.4 V, Other inputs at VCC or GND

VI = 2.5 V or 0.5 V Control inputs 3 pF VO = 2.5 V or 0.5 V A or B ports 10 pF VO = 2.5 V or 0.5 V TDO 8 pF

and I

OZH

OZL

IOH = –24 mA 2 2 IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 IOL = 64 mA 0.55* 0.55

CLK, CLKEN, OE

, TCK A or B ports ±100 ±100 ±100 TDI, TMS 10 10 10 µA

A or B p

include the input leakage current.

Outputs high 0.9 2 2 2 Outputs low 30 38 38 38 Outputs disabled 0.9 2 2 2

±1 ±1 ±1

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Page 21

UNIT

tsuSetup time

thHold time

UNIT

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 13)

SN54ABT8952 SN74ABT8952

MIN MAX MIN MAX

clock

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13)

clock

*On products compliant to MIL-PRF-38535, this parameter is not production tested.

Clock frequency CLKAB or CLKBA 0 100 0 100 MHz Pulse duration CLKAB or CLKBA high or low 3 3 ns

Clock frequency TCK 0 50 0 50 MHz Pulse duration TCK high or low 5 5 ns

Setup time

Hold time

Delay time Power up to TCK↑ 50* 50 ns Rise time VCC power up 1* 1 µs

A before CLKAB↑ or B before CLKBA↑ 4.5 4.5

CLKEN before CLK↑ 4.5 4.5

A after CLKAB↑ or B after CLKBA↑ 0 0

CLKEN after CLK↑ 0 0

SN54ABT8952 SN74ABT8952

MIN MAX MIN MAX

A, B, CLK, CLKEN, or OE before TCK↑ 5 5

TDI before TCK↑

TMS before TCK↑ 6 6

A, B, CLK, CLKEN, or OE after TCK↑ 0 0

TDI after TCK↑

TMS after TCK↑ 0 0

6 6

0 0

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Page 22

SN54ABT8952, SN74ABT8952

(INPUT)

(OUTPUT)

CLKAB or CLKBA

B or A

OEAB

OEBA

B or A

OEAB

OEBA

B or A

(INPUT)

(OUTPUT)

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

TCK↓

A or B

TCK↓

TDO

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 13)

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

3 4.6 5.4 3 6.5 3 6.3

2.5 3.8 4.6 2.5 5.5 2.5 5.3 2 4.1 4.9 2 5.9 2 5.8

2.5 4.7 5.5 2.5 7.1 2.5 6.9

2.5 5.3 6.1 2.5 7.5 2.5 7.3 3 4.5 5.3 3 6.3 3 6.1

PARAMETER

max

PLH

PHL

PZH

PZL

PHZ

PLZ

FROM

CLK A or B 100 130 100 100 MHz

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13)

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

3.5 8 9.5 3.5 12.5 3.5 12 3 7.7 9 3 12 3 11.5

2.5 4.3 5.5 2.5 7 2.5 6.5

2.5 4.2 5.5 2.5 7 2.5 6.5

4.5 8.2 9.5 4.5 12.5 4.5 12

4.5 9 10.5 4.5 13.5 4.5 13

2.5 4.3 5.5 2.5 7 2.5 6.5

2.5 4.9 6 2.5 7.5 2.5 7

3.5 8.4 10.5 3.5 14 3.5 13.5 3 8 10.5 3 13.5 3 13 3 5.9 7 3 9 3 8.5 3 5 6.5 3 8 3 7.5

PARAMETER

max

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

FROM

TCK 50 90 50 50 MHz

SN54ABT8952 SN74ABT8952

UNIT

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Page 23

From Output

Under Test

Input

CL = 50 pF

(see Note A)

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

500 Ω

LOAD CIRCUIT

SN54ABT8952, SN74ABT8952

SCAN TEST DEVICES WITH

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SCBS121D – AUGUST 1992 – REVISED JUL Y 1996

PARAMETER MEASUREMENT INFORMATION

7 V

500 Ω

Open

GND

3 V

0 V

Timing Input

Data Input

TEST S1

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Open

1.5 V

7 V

3 V

0 V

3 V

0 V

Input

PLH

Output

PHL

Output

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.

1.5 V 1.5 V

1.5 V

VOLTAGE WAVEFORMS

Figure 13. Load Circuit and Voltage Waveforms

PHL

1.5 V

PLH

1.5 V1.5 V

3 V

0 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

1.5 V

PZL

PLZ

1.5 V

PZH

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

VOLTAGE WAVEFORMS

1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3.5 V

[

0 V

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Page 24

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SN74ABT8952DL, SN74ABT8952DLR, SN74ABT8952DW, SN74ABT8952DWR Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual