Datasheet SN74ABT841ADBLE, SN74ABT841ADBR, SN74ABT841ADW, SN74ABT841ADWR, SN74ABT841ANT Datasheet (Texas Instruments)

SN54ABT841, SN74ABT841A

10-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

The SN54ABT841 and SN74ABT841A 10-bit
latches are designed specifically for driving highly
capacitive or relatively low-impedance loads.
They are particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus
drivers, and working registers.

The ten transparent D-type latches provide true
data at their outputs.

A buffered output-enable (OE

) input can be used
to place the ten outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.

OE

does not affect the internal operations of the latch. Previously stored data can be retained or new data can

be entered while the outputs are in the high-impedance state.
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT841A is characterized for operation from –40°C to 85°C.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OE

1D
2D
3D
4D
5D
6D
7D
8D
9D

10D

GND

V

CC

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
LE

SN54ABT841 .. . JT OR W PACKAGE

SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

SN54ABT841 . . . FK PACKAGE

(TOP VIEW)

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

3Q
4Q
5Q
NC
6Q
7Q
8Q

3D
4D
5D

NC

6D
7D
8D

426

14 15 16 1718

9D

10D

GND

NC

LE

10Q

9Q

2D1DOE

NC

1Q

2Q

V

CC

NC – No internal connection

SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

OE LE D

Q

L H H H
L HL L
L LX Q

0

H X X Z

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT , PW, and W packages.

EN

1

7

6D

8

7D

9

8D

10

9D

1D

2

1D

6Q

18

7Q

17

8Q

16

9Q

15

1Q

23

3

2D

4

3D

5

4D

6

5D

2Q

22

3Q

21

4Q

20

5Q

19

OE

C1

13

LE

11

10D

10Q

14

logic diagram (positive logic)

OE

To Seven Other Channels

1

13

2

23

LE

1D

C1
1D

1Q

Pin numbers shown are for the DB, DW, JT, NT , PW, and W packages.

SN54ABT841, SN74ABT841A

10-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT841 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT841A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

recommended operating conditions (see Note 3)

SN54ABT841 SN74ABT841A

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –24 –32 mA

I

OL

Low-level output current 48 64 mA

∆t/∆v Input transition rise or fall rate 5 5 ns/V
∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT841 SN74ABT841A

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

V

OH

IOH = –24 mA 2 2

V

V

CC

=

4.5 V

IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55

VOLV

CC

= 4.5

V

IOL = 64 mA 0.55* 0.55

V

V

hys

100 mV

I

I

VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA

I

OZPU

‡

VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA

I

OZPD

‡

VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA

I

OZH

VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA

I

OZL

VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA

I

O

§

VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA

Outputs high 1** 250** 280 250 µA

I

CC

VCC = 5.5 V, IO = 0,

Outputs low 24** 38¶** 45

¶

38¶mA

V

I

=

V

CC

or

GND

Outputs disabled 0.5** 250** 280 250 µA

=

Outputs enabled 1.5 1.5 1.5 mA

∆I

CC

#

V

CC

= 5.5 V,

One input at 3.4 V ,

Outputs disabled 250** 280 250 µA

Other inputs at VCC or GND

Control inputs 1.5 1.5 1.5 mA

C

i

VI = 2.5 V or 0.5 V 4 pF

C

o

VO = 2.5 V or 0.5 V 7 pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT841A.

†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This limit may vary among suppliers.

#

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

VCC = 5 V,

TA = 25°C

SN54ABT841 SN74ABT841A

UNIT

MIN MAX MIN MAX MIN MAX

t

w

Pulse duration, LE high or low 3.3 3.3 3.3 ns

p

High 2.5 2.5 2.5

tsuSetup time, data before LE↓

Low 1.5 1.5 1.5

ns

High 1.5 1.5 1.5

thHold time, data after LE↓

Low 1.5 2 1.5

ns

SN54ABT841, SN74ABT841A

10-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN54ABT841

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

t

PLH

1

†

4.1 5.5 1

†

6.8

t

PHL

D

Q

1.5

†

4 5.5 1.5

†

6.8

ns

t

PLH

1.6

†

4.1

6.6† 1.6†

7.4

t

PHL

LE

Q

2

†

4.6 6.2 2

†

6.8

ns

t

PZH

1 3 4.9

†

1 5.8

t

PZL

OE

Q

2.2 4.1 5.7

†

2.2 6.5

ns

t

PHZ

2

†

4.7 6.2 2

†

7.2

t

PLZ

OE

Q

1.5

†

4.6 6.1 1.5

†

6.6

ns

†

This data sheet limit may vary among suppliers.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

SN74ABT841A

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

TA = 25°C

MIN MAX

UNIT

MIN TYP MAX

t

PLH

1.4

†

4.1 5.5 1.4†6.2

†

t

PHL

D

Q

1.5

†

4 5.5 1.5

†

6.2

ns

t

PLH

2.1

†

4.1 5.9†2.1†6.5

†

t

PHL

LE

Q

2.4

†

4.6 6.2 2.4

†

6.7

ns

t

PZH

1 3 4.7

†

1 5.3

†

t

PZL

OE

Q

2.2 4.1 5.7

†

2.2 6.3

†

ns

t

PHZ

2.6

†

4.7 6.2 2.6

†

7.1

t

PLZ

OE

Q

1.9

†

4.6 6.1 1.9

†

6.5

ns

†

This data sheet limit may vary among suppliers.

SN54ABT841, SN74ABT841A
10-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS196D – FEBRUARY 1991 – REVISED MAY 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V

t

w

Input

VOLTAGE WA VEFORMS

SETUP AND HOLD TIMES

VOLTAGE WA VEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WA VEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WA VEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated