Datasheet SN74ABT7819-20PN, SN74ABT7819-30PH, SN74ABT7819-30PN, SN74ABT7819-10PH, SN74ABT7819-10PN Datasheet (Texas Instruments)

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Page 1

Member of the Texas Instruments Widebus Family

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Read and Write Operations Synchronized to Independent System Clocks

Two Separate 512 × 18 Clocked FIFOs Buffering Data in Opposite Directions

IRA and ORA Synchronized to CLKA

IRB and ORB Synchronized to CLKB

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

Microprocessor Interface Control Logic

Programmable Almost-Full/Almost-Empty Flag

Fast Access Times of 9 ns With a 50-pF Load and Simultaneous Switching Data Outputs

Data Rates up to 100 MHz

Advanced BiCMOS Technology

Package Options Include 80-Pin Quad Flat (PH) and 80-Pin Thin Quad Flat (PN) Packages

PH PACKAGE

(TOP VIEW)

RSTA

PENA

AF/AEA

HFA

IRA

GND

A0 A1

A2 A3

GND

A4 A5

GND

A6 A7

GND

A8 A9

A10

A11

GND

CSA

W/RA

GND

WENA

CLKA

RENA

8079 78 77 76 75 74 73 72 7170 69 68 67 66

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

26 27 28 2930 3132 33 343536 37 38 39

ORA

VCCV

RENB

ORB

CLKB

WENB

GND

W/RB

CSB

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

4025

RSTB PENB AF/AEB HFB IRB GND B0 B1 V

B2 B3 GND B4 B5 GND B6 B7 GND B8 B9 V

B10 B1 1 GND

A12

A13

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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A14

A15

A16

GND

A17

B17

B16

B15

GND

B14

B13

B12

Page 2

SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

PN PACKAGE

(TOP VIEW)

AF/AEA

HFA

IRA

GND

A0 A1

A2 A3

GND

A4 A5

GND

A6 A7

GND

A8 A9

A10

CSA

GND

W/RA

RENA

CLKA

RSTA

PENA

80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 6172

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 4026 27 28 29 30 31 32 33 34 35 36 37 38 39

WENA

ORA

VCCV

ORB

CLKB

RENB

WENB

GND

CSB

W/RB

RSTB

PENB

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AF/AEB HFB IRB GND B0 B1 V

B2 B3 GND B4 B5 GND B6 B7 GND B8 B9 V

B10

A12

A13

A14

A15

A16

GND

A17

B17

B16

GND

A11

GND

B15

B14

B13

B12

GND

B11

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory . Two independent 512 ×18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.

The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The state of the A0–A17 outputs is controlled by CSA are active. The A0–A17 outputs are in the high-impedance state when either CSA written to FIFOA–B from port A on the low-to-high transition of CLKA when CSA is high, and the IRA flag is high. Data is read from FIFOB–A to the A0–A17 outputs on the low-to-high transition of CLKA when CSA

is low, W/RA is low, RENA is high, and the ORA flag is high.

and W/RA. When both CSA and W/RA are low, the outputs

or W/RA is high. Data is

is low, W/RA is high, WENA

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Page 3

A0–A17

PORT-A OPERATION

B0–B17

PORT-B OPERATION

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

description (continued)

The state of the B0–B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs are active. The B0–B17 outputs are in the high-impedance state when either CSB written to FIFOB–A from port B on the low-to-high transition of CLKB when CSB is high, and the IRB flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the low-to-high transition of CLKB when CSB

is low, W/RB is low, RENB is high, and the ORB flag is high.

or W/RB is high. Data is

is low, W/RB is high, WENB

The setup- and hold-time constraints for the chip selects (CSA

, CSB) and write/read selects (W/RA, W/RB) enable write and read operations on memory and are not related to the high-impedance control of the data outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the data outputs.

The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB) and the output-ready flag of FIFOA–B (ORB). When the IR flag of a port is low, the FIFO receiving input from the port is full and writes are disabled to its array . When the OR flag of a port is low , the FIFO that outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high) again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.

The SN74ABT7819 is characterized for operation from 0°C to 70°C.

Function Tables

PORT A

SELECT INPUTS

CLKA CSA W/RA WENA RENA

X H X X X High Z None

↑ L H H X High Z Write A0–A17 to FIFOA–B ↑ L L X H Active Read FIFOB–A to A0–A17

PORT B

SELECT INPUTS

CLKB CSB W/RB WENB RENB

X H X X X High Z None

↑ L H H X High Z Write B0–B17 to FIFOB–A ↑ L L X H Active Read FIFOA–B to B0–B17

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SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

logic symbol

†

CLKA

CSA

W/R

WENA

RENA

RSTA

PENA

IRA

ORA

HFA

AF/AEA

1 2

CLOCK A

OE1

WRITE ENABLE FIFOA–B

READ ENABLE FIFOB–A

RESET FIFO A–B PROGRAM ENABLE

FIFO A–B INPUT-READY

PORT A OUTPUT-READY

PORT A HALF-FULL FIFOA–B

ALMOST-FULL/EMPTY FIFOA–B

FIFO 512 × 18 × 2

SN74ABT7819

PROGRAM ENABLE

ALMOST-FULL/EMPTY

CLOCK B

OE2

WRITE

ENABLE

FIFOB–A

READ

ENABLE

FIFOA–B

RESET FIFO B–A

INPUT-READY

OUTPUT-READY

HALF-FULL

FIFO B–A

PORT B

FIFOB–A

65 66

CLKB

CSB W/RB

WENB

RENB

RSTB PENB

IRB

ORB

HFB

AF/AEB

A10

A11

A12

A13

A14

A15

A16

A17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the PH package.

Data

57 55 54 52 51 49 48 46

45 43 42 40 39 37 36 34

B0 B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11 B12

B13 B14 B15 B16

B17

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Page 5

functional block diagram

PENA RENA

WENA

CSA

W/R

CLKA

RSTA

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

Port-A

Control

Logic

Read

Pointer

ORA

A0–A17

IRA

AF/AEA

HFA

Logic

FIFOB–A

Dual-Port SRAM

Flag

Write

Pointer

512 × 18

FIFOA–B

512 × 18

Dual-Port SRAM

FIFOB–A

Write

Pointer

Flag

Logic

FIFOA–B

IRB AF/AEB HFB

B0–B17

ORB

Read

Pointer

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Port-B

Control

Logic

RSTB CLKB CSB

W/R WENB

RENB PENB

Page 6

SN74ABT7819

I/O

DESCRIPTION

512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

enable logic diagram (positive logic)

CSA

W/RA

WENA

WEN FIFOA–B

A0–A17 (output enable)

RENA

WEN FIFOB–A

B0–B17 (output enable)

REN FIFOA–B

TERMINAL

NAME NO.

A0–A17

AF/AEA 3 O

AF/AEB 62 O

B0–B17

CLKA 76 I

CLKB 69 I

CSA

CSB

†

Terminals listed are for the PH package.

†

7–8, 10–11, 13–14, 16–17, 19–20, 22–23, 25–26, 28–29,

31–32

58–57, 55–54, 52–51, 49–48, 46–45, 43–42, 40–39, 37–36,

34–33

80 I

65 I

I/O Port-A data. The 18-bit bidirectional data port for side A.

I/O Port-B data. The 18-bit bidirectional data port for side B.

REN FIFOB–A

CSB W/RB WENB

RENB

Terminal Functions

FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when X or fewer words or (512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high when FIFOA–B is reset.

FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when X or fewer words or (512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high when FIFOB–A is reset.

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its low-to-high transition and can be asynchronous or coincident to CLKB.

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its low-to-high transition and can be asynchronous or coincident to CLKA.

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from A0–A17 to FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the high-impedance state when CSA

Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from B0–B17 to FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the high-impedance state when CSB

is high.

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Page 7

I/O

DESCRIPTION

TERMINAL

NAME NO.

HFA 4 O

HFB 61 O

IRA 5 O

IRB 60 O

ORA 74 O

ORB 71 O

PENA

PENB

RENA 75 I

RENB 70 I

RSTA

RSTB

WENA 77 I

WENB 68 I

W/RA

W/RB

†

Terminals listed are for the PH package.

†

2 I

63 I

1 I

64 I

79 I

66 I

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

Terminal Functions (Continued)

FIFOA–B half-full flag. HFA is high when FIFOA–B contains 256 or more words and is low when FIFOA–B contains 255 or fewer words. HFA is set low after FIFOA–B is reset.

FIFOB–A half-full flag. HFB is high when FIFOB–A contains 256 or more words and is low when FIFOB–A contains 255 or fewer words. HFB is set low after FIFOB–A is reset.

Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFOA–B is full and writes to its array are disabled. IRA is set low during a FIFOA–B reset and is set high on the second low-to-high transition of CLKA after reset.

Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFOB–A is full and writes to its array are disabled. IRB is set low during a FIFOB–A reset and is set high on the second low-to-high transition of CLKB after reset.

Port-A output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFOB–A is empty and reads from its array are disabled. The last valid word remains on the FIFOB–A outputs when ORA is low. Ready data is present for the A0–A17 outputs when ORA is high. ORA is set low during a FIFOB–A reset and goes high on the third low-to-high transition of CLKA after the first word is loaded to an empty FIFOB–A.

Port-B output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFOA–B is empty and reads from its array are disabled. The last valid word remains on the FIFOA–B outputs when ORB is low. Ready data is present for the B0–B17 outputs when ORB is high. ORB is set low during a FIFOA–B reset and goes high on the third low-to-high transition of CLKB after the first word is loaded to an empty FIFOA–B.

AF/AEA program enable. After FIFOA–B is reset and before a word is written to its array, the binary value on A0–A7 is latched as an AF/AEA offset when PENA

AF/AEB program enable. After FIFOB–A is reset and before a word is written to its array, the binary value on B0–B7 is latched as an AF/AEB offset when PENB

Port-A read enable. A high level on RENA enables data to be read from FIFOB–A on the low-to-high transition of CLKA when CSA

Port-B read enable. A high level on RENB enables data to be read from FIFOA–B on the low-to-high transition of CLKB when CSB

FIFOA–B reset. T o reset FIFOA–B, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RSTA

FIFOB–A reset. T o reset FIFOB–A, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RSTB

Port-A write enable. A high level on WENA enables data on A0–A17 to be written into FIFOA–B on the low-to-high transition of CLKA when W/R

Port-B write enable. A high level on WENB enables data on B0–B17 to be written into FIFOB–A on the low-to-high transition of CLKB when W/R

Port-A write/read select. A high on W/RA enables A0–A17 data to be written to FIFOA–B on a low-to-high transition of CLKA when WENA is high, CSA read from FIFOB–A on a low-to-high transition of CLKA when RENA is high, CSA The A0–A17 outputs are in the high-impedance state when W/R

Port-B write/read select. A high on W/RB enables B0–B17 data to be written to FIFOB–A on a low-to-high transition of CLKB when WENB is high, CSB read from FIFOA–B on a low-to-high transition of CLKB when RENB is high, CSB The B0–B17 outputs are in the high-impedance state when W/R

is low, W/RA is low, and ORA is high.

is low, W/RB is low, and ORB is high.

is low. This sets HFA low, IRA low, ORB low, and AF/AEA high.

is low. This sets HFB low, IRB low, ORA low, and AF/AEB high.

A is high, CSA is low, and IRA is high.

B is high, CSB is low, and IRB is high.

is low, and IRA is high. A low on W/RA enables data to be

is low, and IRB is high. A low on W/RB enables data to be

is low and CLKA is high.

is low and CLKB is high.

is low, and ORA is high.

A is high.

is low, and ORB is high.

B is high.

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SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

CLKA

CLKB

RSTA

IRA

ORB

HFA

AF/AEA

†

FIFOB–A is reset in the same manner.

Figure 1. Reset Cycle for FIFOA–B

214321

4321

†

CLKA

IRA

CSA

W/R

WENA

A0–A17

‡

Written to FIFOA–B

Word 1

‡

Word 2

‡

Figure 2. Write Timing – Port A

Word 3

1 0

‡

Word 4

‡

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Page 9

МММММ

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

CLKB

IRB

CSB

W/R

WENB

B0–B17

†

Written to FIFOB–A

Word 1

†

Word 2

†

Figure 3. Write Timing – Port B

Word 3

1 0

†

Word 4

†

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Page 10

SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

CLKA

CSA

1 0

W/RA

WENA

A0–A17

CLKB

ORB

CSB

W/RB

RENB

1 0

321

B0–B17

Figure 4. ORB-Flag Timing and First Data-Word Fall-Through When FIFOA–B Is Empty

†

Operation of FIFOB–A is identical to that of FIFOA–B.

W1 From FIFOA–B

†

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Page 11

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

CLKB

CSB

W/R

RENB

B0–B17

CLKA

IRA

CSA

WENA

W/R

1 0

From FIFOA–B

1 0

A0–A17

Figure 5. Write-Cycle and IRA-Flag Timing When FIFOA–B Is Full

†

Operation of FIFOB–A is identical to that of FIFOA–B.

To FIFOA–B

†

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Page 12

SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

CLKA

ORA

CSA

W/R

RENA

A0–A17

†

Read from FIFOB–A

CLKB

Word 1

†

Word 2

†

Figure 6. Read Timing – Port A

Word 3

1 0

dis

†

Word 4

†

ORB

CSB

W/R

RENB

B0–B17

‡

Read from FIFOA–B

Word 1

‡

Word 2

‡

Figure 7. Read Timing – Port B

Word 3

dis

‡

Word 4

‡

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Page 13

ÌÌÌ

CLKA

WENA

IRA

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A0 – A17

CLKB

RENB

ORB

B0 – B17

AF/AEA

HFA

NOTES:

W1 WX+1 WX+2 W256 W257 W512–Y W513–Y W513

W1 W2 WY+1

A. CSA, CSB = 0, W/RA = 1, W/RB = 0 B. X is the almost-empty offset and Y is the almost-full of fset for AF/AEA. C. HFB and AF/AEB function in the same manner for FIFO B–A.

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WY+2 W257 W258 W512–X W513–X

SCBS125G – JULY 1992 – REVISED JULY 1998

SN74ABT7819

512 × 18 × 2

Figure 8. FIFOA – B (HFA, AF/AEA) Asynchronous Flag Timing

Page 14

SN74ABT7819

ММММММММММММММ

ПППППППППППП

ОООООООООООООООООООООООО

ПППППППППППППППППППППППП

ППППППП

512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

offset values for AF/AE

The AF/AE flag of each FIFO has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed from the input of the FIFO after it is reset and before a word is written to its memory. An AF/AE flag is high when its FIFO contains X or fewer words or (512 – Y) or more words.

To program the offset values for AF/AEA, PENA

is brought low after FIFOA–B is reset and only when CLKA is low. On the following low-to-high transition of CLKA, the binary value on A0–A7 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PENA

low for another low-to-high transition of CLKA

reprograms Y to the binary value on A0–A7 at the time of the second CLKA low-to-high transition. During the first two CLKA cycles used for offset programming, PENA

low. PENA

can be brought high at any time after the second CLKA pulse used for offset programming returns

can be brought high only when CLKA is

low. A maximum value of 255 can be programmed for either X or Y (see Figure 9). To use the default values of X = Y = 128, PENA The AF/AEB flag is programmed in the same manner, with PENB

must be tied high. No data is stored in FIFOA–B while the AF/AEA offsets are programmed.

enabling CLKB to program the offset values

taken from B0–B7.Figure 8

RESET

CLKA

PENA

IRA

CSA

W/R

WENA

YX and YA0–A7

Figure 9. Programming X and Y Separately for AF/AEA

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Page 15

GND

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high state or power-off state, V Current into any output in the low state, I Input clamp current, I Output clamp current, I Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): PH package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 V to 5.5 V. . . . . . . . . . . . . .

PN package 62°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN NOM MAX UNIT

V V V V I

∆t/∆v Input transition rise or fall rate 5 ns/V T

Supply voltage 4.5 5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

Input voltage 0 V

High-level output current –12 mA Low-level output current 24 mA

Operating free-air temperature 0 70 °C

†

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

OZH

OZL

C C C

‡

All typical values are at VCC = 5 V, TA = 25°C.

The parameters I

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

Control inputs VI = 2.5 V or 0.5 V 6 pF

Flags VO = 2.5 V or 0.5 V 4 pF

A or B ports VO = 2.5 V or 0.5 V 8 pF

and I

OZH

VCC = 4.5 V, II = –18 mA –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 VCC = 5 V, IOH = –3 mA 3 VCC = 4.5 V, IOH = –12 mA 2 VCC = 4.5 V, IOL = 24 mA 0.5 V VCC = 5.5 V, VI = VCC or GND ±1 µA VCC = 5.5 V, VO = 2.7 V 50 µA VCC = 5.5 V, VO = 0.5 V –50 µA VCC = 5.5 V, VO = 2.5 V –40 –100 –180 mA

VCC = 5.5 V, IO = 0,

include the input leakage current.

OZL

Outputs high 15 Outputs low 95 Outputs disabled 15

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Page 16

SN74ABT7819

UNIT

512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 10)

’ABT7819-10 ’ABT7819-12 ’ABT7819-15 ’ABT7819-20 ’ABT7819-30

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

clock

†

To permit the clock pulse to be utilized for reset purposes

Clock frequency 100 80 67 50 33.3 MHz Pulse

duration

Setup time

Hold time

CLKA, CLKB high or low 4.5 4.5 6 8 11 ns A0–A17 before CLKA↑ and

B0–B17 before CLKB↑ CSA before CLKA↑ and

CSB

before CLKB↑

W/RA before CLKA↑ and W/R

B before CLKB↑

WENA before CLKA↑ and WENB before CLKB↑

RENA before CLKA↑ and RENB before CLKB↑

PENA before CLKA↑ and PENB

before CLKB↑

RSTA or RSTB low before first CLKA↑ and CLKB↑

A0–A17 after CLKA↑ and B0–B17 after CLKB↑

CSA after CLKA↑ and CSB

after CLKB↑

W/RA after CLKA↑ and W/R

B after CLKB↑

WENA after CLKA↑ and WENB after CLKB↑

RENA after CLKA↑ and RENB after CLKB↑

PENA after CLKA low and PENB after CLKB low

RSTA or RSTB low after fourth CLKA↑ and CLKB↑

†

2 3 4 5 5

6 6 6 7 7

4 4 4 5 5

5 5 5 5 6

3 3 4 5 5

0 0 0 0 0

2 2 2 2 2

3 3 3 4 4

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Page 17

PARAMETER

UNIT

‡

AF/AEA

AF/AEB

HFA

HFB

A0–A17

B0–B17

A0–A17

B0–B17

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

max

PLH

PHL

PLH

PHL

dis

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

This parameter is measured with a 30-pF load (see Figure 11).

= 50 pF (unless otherwise noted) (see Figure 10)

FROM TO

(INPUT) (OUTPUT)

CLKA

CLKB CLKA↑ A0–A17 3 6 8 4 9 4 10 4 12 4 14 CLKB↑ B0–B17 3 6 8 4 9 4 10 4 12 4 14 CLKA↑ A0–A17 5 CLKB↑ B0–B17 5 CLKA↑ IRA 4 9 4 9 4 10 4 12 4 14 CLKB↑ IRB 4 9 4 9 4 10 4 12 4 14 CLKA↑ ORA 3.5 9 3.5 9 3.5 10 3.5 12 3.5 14 CLKB↑ ORB 3.5 9 3.5 9 3.5 10 3.5 12 3.5 14 CLKA↑ CLKB↑

RSTA AF/AEA 4 12 4 12 4 14 4 15 4 16 ns CLKA↑ CLKB↑

RSTB AF/AEB 4 12 4 12 4 14 4 15 4 16 CLKA↑ HFA 8 17 8 17 8 17 8 18 8 20 CLKB↑

RSTA CLKA↑ HFB 8 17 8 17 8 17 8 18 8 20 CLKB↑

RSTB

CSA

W/RA

CSB

W/RB

CSA

W/RA

CSB

W/RB

’ABT7819-10 ’ABT7819-12 ’ABT7819-15 ’ABT7819-20 ’ABT7819-30

MIN TYP†MAX MIN MAX MIN MAX MIN MAX MIN MAX

100 80 67 50 33.3 MHz

8 17 8 17 8 17 8 18 8 20 8 17 8 17 8 17 8 18 8 20

8 17 8 17 8 17 8 18 8 20 4 12 4 12 4 14 4 15 4 16

2.5 8 2.5 8 2.5 9 2.5 10 2.5 11

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Page 18

SN74ABT7819 512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

PARAMETER MEASUREMENT INFORMATION

7 V

500Ω

From Output

Under Test

Timing

Input

Data

Input

CL = 50 pF

(see Note A)

LOAD CIRCUIT

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

500Ω

Test Point

3 V

0 V

3 V

0 V

Input

Output

Control

PARAMETER S1

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PZL

PZH

PZL

PHZ

dis

PLZ

PLH

PHL

PULSE DURATION

PLZ

Open Closed Open Closed Open Open

1.5 V1.5 V

3 V

0 V

3 V

0 V

Input

PLH

Output

NOTE A: CL includes probe and jig capacitance.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Figure 10. Load Circuit and Voltage Waveforms

PHL

3 V

0 V

Output

Waveform 1

S1 at 7 V

Output

Waveform 2

S1 at Open

1.5 V

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PHZ

1.5 V

VOL + 0.3 V

VOH – 0.3 V

≈ 3.5 V

≈ 0 V

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Page 19

SN74ABT7819

512 × 18 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS125G – JULY 1992 – REVISED JULY 1998

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

LOAD CAPACITANCE

VCC = 5 V

typ + 6

typ + 4

typ + 2

– Propagation Delay Time – ns

TA = 25°C RL = 500 Ω

typ

typ – 2

0 50 100 150

CL – Load Capacitance – pF

160

TA = 75°C CL = 0 pF

140

120

100

– Supply Current – mA

CC(f)

VCC = 5 V

200 250 300

Figure 11

SUPPLY CURRENT

CLOCK FREQUENCY

VCC = 5.5 V

VCC = 4.5 V

10 15 20 25 30 35 40

– Clock Frequency – MHz

clock

45 50 65 70

Figure 12

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55 60

Page 20

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SN74ABT7819-20PN, SN74ABT7819-30PH, SN74ABT7819-30PN, SN74ABT7819-10PH, SN74ABT7819-10PN Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual