Datasheet SN74ABT657ADBLE, SN74ABT657ADBR, SN74ABT657ADW, SN74ABT657ADWR Datasheet (Texas Instruments)
Page 1
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description
Th
e'
ABT657A transceivers have eight
noninverting buffers with parity-generator/
checker circuits and control signals. The
transmit/receive (T/R
) input determines the
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.
Odd or even parity is selected by a logic high or
low level on the ODD/EVEN
input. P ARITY carries
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, P ARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, P ARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN
is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is
low, indicating a parity error.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
T/R
A1
A2
A3
A4
A5
V
CC
A6
A7
A8
ODD/EVEN
ERR
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
SN54ABT657A . . . JT PACKAGE
SN74ABT657A . . . DW OR NT PACKAGE
(TOP VIEW)
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
A3
A2
A1
NC
T/R
OE
B1
ODD/EVEN
ERR
PARITY
NC
B8
B7
B6
4 26
14
15 16 17 18
B5
GND
GND
NC
B4B3B2
A8A7A6
NC
A5
A4
SN54ABT657A . . . FK PACKAGE
(TOP VIEW)
V
CC
NC – No internal connection
Page 2
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT657A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT657A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
NUMBER OF A OR B
INPUTS
I/O
OUTPUTS
INPUTS THAT ARE HIGH
OE T/R ODD/EVEN
PARITY
ERR OUTPUT MODE
L H H
H
Z Transmit
L HL
L
Z Transmit
L LH
H
H Receive
0, 2, 4, 6, 8
L LH
L
L Receive
L LL
H
L Receive
L LL
L
H Receive
L H H
L
Z Transmit
L HL
H
Z Transmit
L LH
H
L Receive
1, 3, 5, 7
L LH
L
H Receive
L LL
H
H Receive
L LL
L
L Receive
Don’t care H X X Z Z Z
Page 3
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
B2
22
B3
21
B4
20
B5
17
B6
16
B1
23
OE
T/R
3 EN1/3G5 [REC]
1
A2
3
A3
4
A4
5
A5
6
A6
8
A7
9
A8
10
B7
15
B8
14
ODD/EVEN
3 EN2 [XMIT]
2 k
5
4, 2
4, 1
ERR
G3
24
N4
11
11
A1
2
12
13
14
15
16
17
18
PARITY
13
12
11
Z11 2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
Page 4
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
T/R
OE
ERR
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN
PARITY
B2
B3
B4
B5
B6
B7
B8
B1
1
2
3
4
5
6
8
9
10
11
24
13
12
23
22
21
20
17
16
15
14
Pin numbers shown are for the DW, JT, and NT packages.
Page 5
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT657A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT657A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT657A SN74ABT657A
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 6
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT657A SN74ABT657A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
V
OH
IOH = –24 mA 2 2
V
V
CC
=
4.5 V
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
VOLV
CC
= 4.5
V
IOL = 64 mA 0.55* 0.55
V
V
hys
100 mV
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1
I
I
A or B ports VCC = 2.1 V to 5.5 V , VI = VCC or GND ±20 ±20 ±20
µ
A
I
OZPU
‡
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V,
OE
= X
±50 ±50 ±50 µA
I
OZPD
‡
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V,
OE
= X
±50 ±50 ±50 µA
I
OZH
§
VCC = 2.1 V to 5.5 V, VO = 2.7 V,
OE
≥ 2 V
10 10 10 µA
I
OZL
§
VCC = 2.1 V to 5.5 V, VO = 0.5 V,
OE
≥ 2 V
–10 –10 –10 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high 50 50 50 µA
I
O
¶
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
=
Outputs high 250 250 250 µA
I
CC
V
CC
= 5.5 V,
IO = 0,
Outputs low 40 40 40 mA
VI = VCC or GND
Outputs disabled 250 250 250 µA
p
VCC = 5.5 V,
One input at 3.4 V ,
Outputs enabled 1.5 1.5 1.5
∆I
CC
#
Data inputs
,
Other inputs at
VCC or GND
Outputs disabled 0.25 0.25 0.25 mA
Control inputs
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1.5 1.5 1.5
C
i
Control inputs VI = 2.5 V or 0.5 V 4 pF
C
io
A or B ports VO = 2.5 V or 0.5 V 10 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
The parameters I
OZH
and I
OZL
include the input leakage current.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 7
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABT657A SN74ABT657A
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
t
PLH
1 3.2 4.2 1 5 1 4.6
t
PHL
A or B
B or A
1 2.8 3.8 1 4.5 1 4.3
ns
t
PLH
1.8 4.8 6.3 1.8 8.5 1.8 8.1
t
PHL
A
PARITY
2.3 4.9 6.4 2.3 8.1 2.3 7.7
ns
t
PLH
1.1 3.3 4.2 1.1 5.3 1.1 4.9
t
PHL
ODD/EVEN
PARITY, ERR
1.3 3.4 4.5 1.3 5.1 1.3 4.9
ns
t
PLH
1.6 4.7 6.5 1.6 8.4 1.6 7.9
t
PHL
B
ERR
2.1 4.9 6.9 2.1 8 2.1 7.8
ns
t
PLH
2 4.8 6.3 2 8.1 2 7.7
t
PHL
PARITY
ERR
2.1 4.9 6.7 2.1 8 2.1 7.5
ns
t
PZH
1.4 4 5.4 1.4 6.8 1.4 6.5
t
PZL
OE
A, B, PARITY
1.7 4.1 5.8 1.7 6.7 1.7 6.5
ns
t
PZH
1.8 4.1 5.4 1.8 6.9 1.8 6.6
t
PZL
OE
ERR
3.3 6.2 7.6 3.3 9.7 3.3 9.2
ns
t
PHZ
A, B, PARITY, or
2.4 4.2 5.6 2.4 6.3 2.4 6.2
t
PLZ
OE
,, ,
ERR
1.8 4.2 6.2 1.8 8.9 1.8 7.8
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 8
SN54ABT657A, SN74ABT657A
OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS
AND 3-STATE OUTPUTS
SCBS192E – JANUARY 1991 – REVISED JUNE 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
Page 9
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