Datasheet SN74ABT240AN, SN74ABT240APWLE, SN74ABT240APWR, SN74ABT240ADBLE, SN74ABT240ADBR Datasheet (Texas Instruments)

SN54ABT240, SN74ABT240A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package

description

These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. Together with the SN54ABT241,
SN74ABT241A, SN54ABT244, and
SN74ABT244A, these devices provide the choice
of selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE
OE and OE inputs.

) inputs, and complementary

SN54ABT240 ...J OR W PACKAGE

SN74ABT240A . . . DB, DW, N, OR PW PACKAGE

SN54ABT240 . . . FK PACKAGE

1A2
2Y3
1A3
2Y2
1A4

(TOP VIEW)

1OE

1

1A1

2

2Y4

3

1A2

4

2Y3

5

1A3

6

2Y2

7

1A4

8
9

2Y1

GND

10

(TOP VIEW)

2Y4

3212019

4
5
6
7
8

910111213

2Y1

1A1

GND

20
19
18
17
16
15
14
13
12
11

1OE

V

2A1

CC

1Y4

V

CC

2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1

18
17
16
15
14

2A2 2OE

1Y1
2A4
1Y2
2A3
1Y3

The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE inputs.
When OE is low, the devices pass inverted data from the A inputs to the Y outputs. When OE is high, the outputs
are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT240 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT240A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

FUNCTION TABLE

(each buffer)

INPUTS

OE A

L H L
L LH

H X Z

OUTPUT

Y

logic symbol

1OE

1A1
1A2
1A3
1A4

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

1

2
4
6
8

EN

18
16
14
12

1Y1
1Y2
1Y3
1Y4

2OE

2A1
2A2
2A3
2A4

logic diagram (positive logic)

1

1OE

218

1A1

416

1A2

1Y1

1Y2

2OE

2A1

2A2

19

11
13
15
17

19

11 9

13 7

EN

2Y1

2Y2

9

2Y1

7

2Y2

5

2Y3

3

2Y4

614

1A3

812

1A4

2

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1Y3

1Y4

15 5

2A3

17 3

2A4

2Y3

2Y4

UNIT

SN54ABT240, SN74ABT240A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT240 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

SN74ABT240A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ABT240 SN74ABT240A

MIN MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

CC

0 V

CC

V

†

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3

SN54ABT240, SN74ABT240A

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

VOLV

V

V

V

I

V

CC

GND

§

,

OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT240 SN74ABT240A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

V

hys

I

I

I

OZH

I

OZL

I

off

I

CEX

‡

I

O

I

CC

Data

∆I

C
C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

inputs

CC

Control
inputs

i
o

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

VCC = 5.5 V, IO = 0,

=

or

VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 4 pF
VO = 2.5 V or 0.5 V 7.5 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

Outputs high 1 250 250 250 µA
Outputs low 24 30 30 30 mA
Outputs disabled 0.5 250 250 250 µA

Outputs enabled 1.5 1.5 1.5

Outputs disabled 0.05 0.05 0.05

1.5 1.5 1.5

mA

4

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A

Y

ns

OE

Y

ns

OE

Y

ns

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ABT240, SN74ABT240A

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

TO

(OUTPUT)

TO

(OUTPUT)

SN54ABT240

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.9 4.3 0.8 5.5

1.6 3.1 4.5 1 5.5

1.1 3.1 5.8 0.8 7.5

1.1 2.7 6.2 0.8 7.7

1.8 4.6 5.9 1.7 7

1.6 4 5.9 1.3 7.2

SN74ABT240A

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.9 4.1 1 4.8

1.6 3.1 4.6 1.6 4.8

1.1 3.1 4.7 1.1 5.2

1.1 2.7 5.8 1.1 6.2

1.8 4.6 5.7 1.8 6.4

1.6 4 5.4 1.6 5.8

MIN MAX

MIN MAX

UNIT

UNIT

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5

SN54ABT240, SN74ABT240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS098H – JANUARY 1991 – REVISED JANUARY 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Output

Control

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

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