Datasheet SN74ABT18504PM Datasheet (Texas Instruments)

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SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
Members of the Texas Instruments
Family of Testability Products
Members of the Texas Instruments
Widebus
Family
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
Two Boundary-Scan Cells per I/O for
Greater Flexibility
State-of-the-Art
Significantly Reduces Power Dissipation
EPIC-ΙΙB
BiCMOS Design
A3A2A1
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ
– Parallel Signature Analysis at Inputs With
Masking Option
– Pseudo-Random Pattern Generation
From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat
Pack Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat Pack Using 25-mil Center-to-Center Spacings
SN54ABT18504 . . . HV PACKAGE
GND
OEBA
LEBA
(TOP VIEW)
CC
VNCTMS
TDO
CLKBA
CLKENBA
B1
Instruction Set
B3
GNDB2B4
87 65493168672
10
A4
11
A5
12
A6
A7 A8 A9
A10
NC
CC
A11 A12 A13
A14 A15 A16
13 14 15 16 17 18 19 20 21 22 23 24 25 26
28 29 30 31 32 33 34
A19
A17
A18
GND
GND
V
GND
NC – No internal connection
A20
CLKENAB
35 36 37 38 39
NC
TDI
CLKAB
66 652764 63 62 61
CC
V
TCK
LEAB
OEAB
40 41 42 43
B20
B19
GND
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
B18
B5 B6 B7 GND B8 B9 B10 V
CC
NC B11 B12 B13 B14 GND B15 B16 B17
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of T exas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Copyright 1993, Texas Instruments Incorporated
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
A4 A5 A6
GND
A7 A8 A9
A10
V
CC
A11 A12 A13
GND
A14 A15 A16
SN74ABT18504 ...PM PACKAGE
A1
A3
A2
63 62 61 60 5964 58 56 55 5457 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
18 19
GND
OEBA
21 22 23 24
20
(TOP VIEW)
CC
LEBA
TDO
V
CLKENBAB1B2
TMS
CLKBA
53 521751 50 49
25 26 27 28 29
GND
30 31 32
B3
B4
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
B5 B6 B7 GND B8 B9 B10 V
CC
B11 B12 B13 B14 GND B15 B16 B17
CC
A17
A18
A19
GND
A20
TDI
CLKAB
B20
B19
V
TCK
LEAB
OEAB
GND
B18
CLKENAB
description
The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments SCOPE testability IC family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the T AP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB is low , A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low , the B outputs are active. When OEAB
is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
and OEBA), latch-enable (LEAB and LEBA),
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Page 3
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
description (continued)
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally , the test circuitry can perform other testing functions such as parallel signature analysis on data inputs and pseudo-random pattern generation from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary scan cells (BSCs) for each I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT instruction is also included to ease the testing of memories and other circuits where a binary count addressing scheme is useful.
The SN54ABT18504 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT18504 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(normal mode, each register)
INPUTS
OEAB LEAB CLKENAB CLKAB A
L L L L X B L LL LL L LL HH L LH XXB L HX XLL L HX XHH
H X X X X Z
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKENBA
Output level before the indicated steady-state input conditions were established.
, and CLKBA.
OUTPUT
B
0
0
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
functional block diagram
Boundary-Scan Register
CLKENAB
LEAB
CLKAB
OEAB
CLKENBA
LEBA
CLKBA
OEBA
A1
22
27
23
28
54
59
55
60
62
1 of 20 Channels
C1 1D
C1
1D
C1 1D
C1 1D
53
B1
V
CC
24
TDI
V
CC
56
TMS
TAP
26
TCK
Pin numbers shown are for the PM package.
Controller
Bypass Register
Boundary-Control
Register
Identification
Register
Instruction
Register
58
TDO
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20-BIT UNIVERSAL BUS TRANSCEIVERS
Terminal Functions
PIN NAME DESCRIPTION
A1–A20 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1–B20 Normal-function B-bus I/O ports. See function table for normal-mode logic.
CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.
CLKENAB,
CLKENBA
GND Ground
LEAB, LEBA Normal-function latch enables. See function table for normal-mode logic.
OEAB, OEBA Normal-function output enables. See function table for normal-mode logic.
TCK
TDI
TDO
TMS V
CC
Normal-function clock enables. See function table for normal-mode logic.
T est clock. One of four pins required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to the test clock. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
T est data input. One of four pins required by IEEE Standard 1149.1-1990. The test data input is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
T est data output. One of four pins required by IEEE Standard 1149.1-1990. The test data output is the serial output for shifting data through the instruction register or selected data register.
T est mode select. One of four pins required by IEEE Standard 1149.1-1990. The test mode select input directs the device through its test access port (TAP) controller states. An internal pullup forces TMS to a high level if left unconnected.
Supply voltage
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
test architecture
Serial test information is conveyed by means of a 4-wire test bus or test access port (T AP), that conforms to IEEE Standard 1 149.1-1990. Test instructions, test data, and test control signals are all passed along this serial test bus. The T AP controller monitors two signals from the test bus, namely TCK and TMS. The function of the T AP controller is to extract the synchronization (TCK) and state control (TMS) signals from the test bus and generate the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the T AP controller state diagram.
The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle.
The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship between the test bus, the T AP controller , and the test registers. As illustrated, the device contains an 8-bit instruction register and four test data registers: an 88-bit boundary-scan register, a 23-bit boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = L
Run-Test/Idle Select-DR-Scan
TMS = L
Capture-DR
TMS = L
Shift-DR
TMS = L
TMS = H
TMS = H
Exit1-DR
TMS = L
Pause-DR
TMS = L
TMS = H
Exit2-DR
TMS = H
TMS = HTMS = H
TMS = H TMS = H
TMS = L
TMS = L
Select-IR-Scan
TMS = H
TMS = L
Capture-IR
TMS = L
Shift-IR
TMS = L
TMS = H
TMS = H
Exit1-IR
TMS = L
Pause-IR
TMS = L
TMS = H
Exit2-IR
TMS = H
Update-DR
TMS = LTMS = H
Update-IR
TMS = LTMS = H
Figure 1. TAP Controller State Diagram
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Page 7
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
state diagram description
The test access port (TAP) controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard
1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the T AP controller consists of sixteen states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is defined as a state the T AP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths though the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data registers may also be reset to their power-up values.
The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.
For the ABT18504, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Each bit in the boundary-scan register is reset to logic 0 except bits 87–86, which are reset to logic 1. The boundary-control register is reset to the binary value 00000000000000000000010, which selects the PSA test operation with no input masking.
Run-Test/Idle
The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test operations. The Run-Test/Idle state can also be entered following data register or instruction register scans. Run-Test/Idle is provided as a stable state in which the test logic may be actively running a test or can be idle.
The test operations selected by the boundary-control register are performed while the T AP controller is in the Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits either of these states on the next TCK cycle. These states are provided to allow the selection of either data register scan or instruction register scan.
Capture-DR
When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK upon which the T AP controller exits the Capture-DR state.
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
state diagram description (continued)
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states used to end a data register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state provides the capability of suspending and resuming data register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK following entry to the Update-DR state.
Capture-IR
When an instruction register scan is selected, the T AP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK upon which the TAP controller exits the Capture-IR state.
For the ABT18504, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK upon which the T AP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states used to end an instruction register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
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SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
state diagram description (continued)
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the T AP controller can remain indefinitely. The Pause-IR state provides the capability of suspending and resuming instruction register scan operations without loss of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR state.
register overview
With the exception of the bypass and device identification registers, any test register can be thought of as a serial shift register with a shadow latch on each bit. The bypass and device identification registers differ in that they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and is used to tell the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 4 lists the instructions supported by the ABT18504. The even-parity feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value will be shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 10000001, which selects the IDCODE instruction.
The instruction register order of scan is illustrated in Figure 2.
Bit 7 Parity (MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Figure 2. Instruction Register Order of Scan
Bit 0
(LSB)
TDOTDI
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
data register description
boundary-scan register
The boundary-scan register (BSR) is 88 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output data). The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, the value of each BSC is reset to logic 0 except BSCs 87–86, which are reset to logic 1.
The boundary-scan register order of scan is from TDI through bits 87–0 to TDO. Table 1 shows the boundary-scan register bits and their associated device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
87 OEAB 79 A20-I 59 A20-O 39 B20-I 19 B20-O 86 OEBA 78 A19-I 58 A19-O 38 B19-I 18 B19-O 85 CLKAB 77 A18-I 57 A18-O 37 B18-I 17 B18-O 84 CLKBA 76 A17-I 56 A17-O 36 B17-I 16 B17-O 83 CLKENAB 75 A16-I 55 A16-O 35 B16-I 15 B16-O 82 CLKENBA 74 A15-I 54 A15-O 34 B15-I 14 B15-O 81 LEAB 73 A14-I 53 A14-O 33 B14-I 13 B14-O 80 LEBA 72 A13-I 52 A13-O 32 B13-I 12 B13-O –– –– 71 A12-I 51 A12-O 31 B12-I 11 B12-O –– –– 70 A11-I 50 A11-O 30 B11-I 10 B11-O –– –– 69 A10-I 49 A10-O 29 B10-I 9 B10-O –– –– 68 A9-I 48 A9-O 28 B9-I 8 B9-O –– –– 67 A8-I 47 A8-O 27 B8-I 7 B8-O –– –– 66 A7-I 46 A7-O 26 B7-I 6 B7-O –– –– 65 A6-I 45 A6-O 25 B6-I 5 B6-O –– –– 64 A5-I 44 A5-O 24 B5-I 4 B5-O –– –– 63 A4-I 43 A4-O 23 B4-I 3 B4-O –– –– 62 A3-I 42 A3-O 22 B3-I 2 B3-O –– –– 61 A2-I 41 A2-O 21 B2-I 1 B2-O –– –– 60 A1-I 40 A1-O 20 B1-I 0 B1-O
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
boundary-control register
The boundary-control register (BCR) is 23 bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include pseudo-random pattern generation (PRPG), parallel signature analysis (PSA) with input masking, and binary count up (COUNT). Table 5 shows the test operations that are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 00000000000000000000010, which selects the PSA test operation with no input masking.
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SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
data register description (continued)
The boundary-control register order of scan is from TDI through bits 22–0 to TDO. Table 2 shows the boundary-control register bits and their associated test control signals.
Table 2. Boundary Control Register Configuration
BCR BIT
NUMBER
22 MASK20 12 MASK10 2 OPCODE2 21 MASK19 11 MASK9 1 OPCODE1 20 MASK18 10 MASK8 0 OPCODE0 19 MASK17 9 MASK7 –– –– 18 MASK16 8 MASK6 –– –– 17 MASK15 7 MASK5 –– –– 16 MASK14 6 MASK4 –– –– 15 MASK13 5 MASK3 –– –– 14 MASK12 4 MASK2 –– –– 13 MASK11 3 MASK1 –– ––
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
TEST
CONTROL
SIGNAL
bypass register
The bypass register is a one-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation.
During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in Figure 3.
Bit 0
TDOTDI
Figure 3. Bypass Register Order of Scan
device identification register
The device identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device.
During Capture-DR, the binary value 00000000000000000111000000101111 (0000702F, hex) is captured in the device identification register to identify this device as Texas Instruments SN54/74ABT18504, version 0.
The device identification register order of scan is from TDO through bits 31–0 to TDO. T able 3 shows the device identification register bits and their significance.
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SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
Table 3. Device Identification Register Configuration
IDR BIT
NUMBER
31 VERSION3 27 PARTNUMBER15 11 MANUFACTURER10 30 VERSION2 26 PARTNUMBER14 10 MANUFACTURER09 29 VERSION1 25 PARTNUMBER13 9 MANUFACTURER08 28 VERSION0 24 PARTNUMBER12 8 MANUFACTURER07 –– –– 23 PARTNUMBER11 7 MANUFACTURER06 –– –– 22 PARTNUMBER10 6 MANUFACTURER05 –– –– 21 PARTNUMBER09 5 MANUFACTURER04 –– –– 20 PARTNUMBER08 4 MANUFACTURER03 –– –– 19 PARTNUMBER07 3 MANUFACTURER02 –– –– 18 PARTNUMBER06 2 MANUFACTURER01 –– –– 17 PARTNUMBER05 1 MANUFACTURER00 –– –– 16 PARTNUMBER04 0 LOGIC1 –– –– 15 PARTNUMBER03 –– –– –– –– 14 PARTNUMBER02 –– –– –– –– 13 PARTNUMBER01 –– –– –– –– 12 PARTNUMBER00 –– ––
Note that for TI products, bits 11– 0 of the device identification register always contains the binary value 00000010111 1 (02F , hex).
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
Table 4. Instruction Register Opcodes
BINARY CODE
BIT 7 BIT 0
MSB LSB
00000000 EXTEST Boundary scan Boundary scan Test 10000001 IDCODE Identification read Device identification Normal 10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal
0000001 1 INTEST Boundary scan Boundary scan Test 10000100 BYP ASS 00000101 BYPASS
00000110 HIGHZ Control boundary to high impedance Bypass Modified test
100001 11 CLAMP Control boundary to 1/0 Bypass Test 10001000 BYP ASS 00001001 RUNT Boundary run test Bypass Test 00001010 READBN Boundary read Boundary scan Normal
1000101 1 READBT Boundary read Boundary scan Test
00001 100 CELLTST Boundary self test Boundary scan Normal
10001 101 TOPHIP Boundary toggle outputs Bypass Test
10001 110 SCANCN Boundary-control register scan Boundary control Normal
00001 111 SCANCT Boundary-control register scan Boundary control T est
All others BYPASS Bypass scan Bypass Normal
Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ′ABT18504.
SCOPE OPCODE DESCRIPTION
‡ ‡
SELECTED DATA
REGISTER
Bypass scan Bypass Normal Bypass scan Bypass Normal
Bypass scan Bypass Normal
† † † † † † † † † † †
MODE
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SCBS108B – AUGUST 1992 – REVISED JUNE 1993
instruction register opcode description
The instruction register opcodes are shown in Table 4. The following descriptions detail the operation of each instruction.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The boundary-scan register is selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The boundary-scan register is selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the normal mode.
control boundary to high impedance
This instruction conforms to the IEEE P1 149.1A HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE P1 149.1A CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output pins. The device operates in the test mode.
boundary run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the boundary-control register is executed during Run-T est/Idle. The five test operations decoded by the boundary-control register are: sample inputs/toggle outputs (TOPSIP), pseudo-random pattern generation (PRPG), parallel signature analysis (PSA), simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT).
boundary read
The boundary-scan register is selected in the scan path. The value in the boundary-scan register remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation.
boundary self test
The boundary-scan register is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way , the contents of the shadow latches can be read out to verify the integrity of both shift register and shadow latch elements of the boundary-scan register. The device operates in the normal mode.
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instruction register opcode description (continued)
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of TCK in Run-T est/Idle, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs. The device operates in the test mode.
boundary-control register scan
The boundary-control register is selected in the scan path. The value in the boundary-control register remains unchanged during Capture-DR. This operation must be performed prior to a boundary run test operation in order to specify which test operation is to be executed.
Table 5. Boundary-Control Register Opcodes
BINARY CODE
BIT 2 BIT 0
MSB LSB
X00 Sample inputs/toggle outputs (TOPSIP) X01 Pseudo-random pattern generation/40-bit mode (PRPG) X10 Parallel signature analysis/40-bit mode (PSA)
011 Simultaneous PSA and PRPG/20-bit mode (PSA/PRPG) 111 Simultaneous PSA and binary count up/20-bit mode (PSA/COUNT)
DESCRIPTION
boundary-control register opcode description
The boundary-control register opcodes are decoded from BCR bits 2–0 as shown in Table 5. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
In general, while the control input BSCs (bits 87–80) are not included in the toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 87–86 of the BSR) control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are only valid when the device is operating in one direction of data flow (that is, OEAB
PSA input masking
Bits 22 – 3 of the boundary-control register are used to specify device input pins to be masked from PSA operations. Bit 22 selects masking for device input pin A20 during A-to-B data flow or for device input pin B20 during B-to-A data flow. Bit 3 selects masking for device input pins A1 or B1 during A-to-B or B-to-A data flow, respectively . Bits intermediate to 22 and 3 mask corresponding device input pins in order from most significant to least significant, as indicated in Table 2. When the mask bit which corresponds to a particular device input has a logic 1 value, the device input pin is masked from any PSA operation, meaning that the state of the device input pin is ignored and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding device input is not masked from the PSA operation.
OEBA). Otherwise, the bypass instruction is operated.
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boundary-control register opcode description (continued)
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of TCK and is then updated in the shadow latches and applied to the associated device output pins on each falling edge of TCK.
pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. This data is also updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Figures 4 and 5 illustrate the 40-bit linear-feedback shift-register algorithms through which the patterns are generated. An initial seed value should be scanned into the boundary-scan register prior to performing this operation. A seed value of all zeroes will not produce additional patterns.
A19-I
A9-I
B19-O
=
B9-O
B18-O B17-O B16-O B15-O B14-O B13-O B12-O B11-OB20-O
B8-O B7-O B6-O B5-O B4-O B3-O B2-O B1-OB10-O
A17-I A16-I A15-I A14-I A13-I A12-I A11-IA18-IA20-I
A7-I A6-I A5-I A4-I A3-I A2-I A1-IA8-IA10-I
Figure 4. 40-Bit PRPG Configuration (OEAB = 0, OEBA = 1)
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B19-I
B9-I
A19-O
=
A9-O
A18-O A17-O A16-O A15-O A14-O A13-O A12-O A11-OA20-O
A8-O A7-O A6-O A5-O A4-O A3-O A2-O A1-OA10-O
B17-I B16-I B15-I B14-I B13-I B12-I B11-IB18-IB20-I
B7-I B6-I B5-I B4-I B3-I B2-I B1-IB8-IB10-I
Figure 5. 40-Bit PRPG Configuration (OEAB = 1, OEBA = 0)
16
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SCAN TEST DEVICES WITH
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SCBS108B – AUGUST 1992 – REVISED JUNE 1993
boundary-control register opcode description (continued)
parallel signature analysis (PSA)
Data appearing at the selected device input pins is compressed into a 40-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 6 and 7 illustrate the 40-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the boundary-scan register prior to performing this operation.
=
=
MASKX
A19-I
A9-I
B19-O
B9-O
A17-I A16-I A15-I A14-I A13-I A12-I A11-IA18-IA20-I
A7-I A6-I A5-I A4-I A3-I A2-I A1-IA8-IA10-I
B18-O B17-O B16-O B15-O B14-O B13-O B12-O B11-OB20-O
B8-O B7-O B6-O B5-O B4-O B3-O B2-O B1-OB10-O
Figure 6. 40-Bit PSA Configuration (OEAB = 0, OEBA = 1)
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=
=
MASKX
B19-I
B9-I
A19-O
A9-O
B17-I B16-I B15-I B14-I B13-I B12-I B11-IB18-IB20-I
B7-I B6-I B5-I B4-I B3-I B2-I B1-IB8-IB10-I
A18-O A17-O A16-O A15-O A14-O A13-O A12-O A11-OA20-O
A8-O A7-O A6-O A5-O A4-O A3-O A2-O A1-OA10-O
Figure 7. 40-Bit PSA Configuration (OEAB = 1, OEBA = 0)
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boundary-control register opcode description (continued)
simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into a 20-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs andapplied to the inputs of the normal on-chip logic. At the same time, a 20-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. Figures 8 and 9 illustrate the 20-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial seed value should be scanned into the boundary-scan register prior to performing this operation. A seed value of all zeroes will not produce additional patterns.
=
=
MASKX
A19-I
A9-I
B19-O
A17-I A16-I A15-I A14-I A13-I A12-I A11-IA18-IA20-I
A7-I A6-I A5-I A4-I A3-I A2-I A1-IA8-IA10-I
B18-O B17-O B16-O B15-O B14-O B13-O B12-O B11-OB20-O
B9-O
B8-O B7-O B6-O B5-O B4-O B3-O B2-O B1-OB10-O
Figure 8. 20-Bit PSA/PRPG Configuration (OEAB = 0, OEBA = 1)
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B17-I B16-I B15-I B14-I B13-I B12-I B11-IB18-IB20-I B19-I
=
=
MASKX
B7-I B6-I B5-I B4-I B3-I B2-I B1-IB8-IB10-I B9-I
A18-O A17-O A16-O A15-O A14-O A13-O A12-O A11-OA20-O A19-O
A8-O A7-O A6-O A5-O A4-O A3-O A2-O A1-OA10-O A9-O
Figure 9. 20-Bit PSA/PRPG Configuration (OEAB = 1, OEBA = 0)
20
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SCBS108B – AUGUST 1992 – REVISED JUNE 1993
boundary-control register opcode description (continued)
simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into a 20-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same time, a 20-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge of TCK. Figures 10 and 11 illustrate the 20-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the boundary-scan register prior to performing this operation.
=
MASKX
MSB
A19-I
A9-I
B19-O
A17-I A16-I A15-I A14-I A13-I A12-I A11-IA18-IA20-I
A7-I A6-I A5-I A4-I A3-I A2-I A1-IA8-IA10-I
B18-O B17-O B16-O B15-O B14-O B13-O B12-O B11-OB20-O
LSB
=
B9-O
B8-O B7-O B6-O B5-O B4-O B3-O B2-O B1-OB10-O
Figure 10. 20-Bit PSA/COUNT Configuration (OEAB = 0, OEBA = 1)
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MSB
MASKX
A18-O A17-O A16-O A15-O A14-O A13-O A12-O A11-OA20-O A19-O
B17-I B16-I B15-I B14-I B13-I B12-I B11-IB18-IB20-I B19-I
B7-I B6-I B5-I B4-I B3-I B2-I B1-IB8-IB10-I B9-I
=
=
A8-O A7-O A6-O A5-O A4-O A3-O A2-O A1-OA10-O A9-O
LSB
Figure 11. 20-Bit PSA/COUNT Configuration (OEAB = 1, OEBA = 0)
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timing description
All test operations of the ABT18504 are synchronous to the test clock (TCK). Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is illustrated in Figure 12. In this example, the TAP controller begins in the T est-Logic-Reset state and is advanced through its states as necessary to perform one instruction register scan and one data register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used to output serial data. The T AP controller is then returned to the T est-Logic-Reset state. Table 6 explains the operation of the test circuitry during each TCK cycle.
Table 6. Explanation of Timing Example
TCK
CYCLE(S)
1 Test-Logic-Reset
2 Run-Test/Idle
3 Select-DR-Scan
4 Select-IR-Scan
5 Capture-IR
6 Shift-IR
7–13 Shift-IR
14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. 16 Select-DR-Scan
17 Capture-DR
18 Shift-DR
19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR In general, the selected data register is updated with the new data on the falling edge of TCK. 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset Test operation completed
TAP STATE
AFTER TCK
DESCRIPTION
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state.
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state.
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the instruction register scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state.
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.
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МММММ
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SCBS108B – AUGUST 1992 – REVISED JUNE 1993
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TCK
TMS
TDI
TDO
TAP
Controller
State
Run-Test/Idle
Test-Logic-Reset
Select-DR-Scan
Capture-IR
Select-IR-Scan
Shift-IR
3-State (TDO) or Don’t Care (TDI)
Exit1-IR
Update-IR
Capture-DR
Select-DR-Scan
Shift-DR
Exit1-DR
Update-DR
Select-IR-Scan
Select-DR-Scan
Figure 12. Timing Example
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Input voltage range, VI (I/O ports) (see Note 1) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT18504 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I Output clamp current, I
Continuous current through VCC 576 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through GND 1152 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
2. For the SN74ABT18504 (PM package), the power derating factor for ambient temperatures greater than 55°C is –10.5 mW/°C.
(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
SN74ABT18504 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
= 55°C (in still air) (see Note 2) 885 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Test-Logic-Reset
24
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UNIT
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recommended operating conditions (see Note 3)
SN54ABT18504 SN74ABT18504
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
t/∆v Input transition rise or fall rate 10 10 ns/V T
A
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
Supply voltage 4.5 5.5 4.5 5.5 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 0 V High-level output current –24 –32 mA Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
µ
I
V
V
GND
µ
,
V
CC
5.5 V,
orts
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SCBS108B – AUGUST 1992 – REVISED JUNE 1993
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54ABT18504 SN74ABT18504
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
OL
I
I
IH
I
IL
I
OZH
I
OZL
I
OZPU
I
OZPD
I
off
I
CEX
I
O
I
CC
I
CC
C
i
C
io
C
o
All typical values are at VCC = 5 V.
On products compliant to MIL-STD-883, Class B, this parameter does not apply.
§
For I/O ports, the parameters I
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = – 3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = – 3 mA 3 3 3 VCC = 4.5 V, IOH = – 24 mA 2 2 VCC = 4.5 V, IOH = – 32 mA 2
= 4.5
CC
VCC = 5.5 V,
=
or
I
CC
VCC = 5.5 V, VI = V
CC
VCC = 5.5 V, VI = GND
§
VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
§
VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA VCC = 0 to 2 V,
VO = 2.7 V or 0.5 V VCC = 0 to 2 V,
VO = 2.7 V or 0.5 V VCC = 0, VI or VO 4.5 V ±100 ±450 ±100 µA VCC = 5.5 V,
VO = 5.5 V VCC = 5.5 V, VO = 2.5 V –50 –110 –200 –50 –200 –50 –200 mA
V
= 5.5 V IO = 0, VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
#
Other inputs at VCC or GND VI = 2.5 V or 0.5 V Control inputs 3 pF VO = 2.5 V or 0.5 V A or B ports 10 pF VO = 2.5 V or 0.5 V TDO 8 pF
IOL = 48 mA 0.55 0.55 IOL = 64 mA 0.55
CLK, CLKEN,
, TCK
LE, OE A or B ports ±100 ±100 ±100
TDI, TMS 10 10 10 µA
TDI, TMS –150 –150 –150 µA
OE = 0.8 V
OE = 0.8 V
Outputs high 50 50 50 µA
Outputs high 3.5 5.5 5.5 5.5 Outputs low 36 40 40 40 mA Outputs disabled 2.9 5 5 5
include the input leakage current.
OZL
OZH
A or B p
and I
±1 ±1 ±1
±50 ±50 ±50 µA
±50 ±50 ±50 µA
50 50 50 µA
2
0.55
A
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 27
SN54ABT18504, SN74ABT18504
UNIT
twPulse duration
ns
tsuSetup time
A before LEAB or B before LEBA
ns
UNIT
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 13)
SN54ABT18504 SN74ABT18504
MIN MAX MIN MAX
f
clock
t
h
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13)
f
clock
t
w
t
su
t
h
t
d
t
r
Clock frequency, CLKAB or CLKBA 0 100 0 100 MHz
CLKAB or CLKBA high or low 4 4 LEAB or LEBA CLK high or low 3.5 3.5 A before CLKAB or B before CLKBA 4 4
p
CLKEN before CLK 4 4 A after CLKAB or B after CLKBA 0 0
Hold time
Clock frequency, TCK 0 50 0 50 MHz Pulse duration TCK high or low 8 8 ns
Setup time
Hold time
Delay time Power up to TCK 50 50 ns Rise time VCC power up 1 1 µs
A after LEAB or B after LEBA CLKEN after CLK 0 0
A, B, CLK, LE, or OE before TCK 4.5 4.5 TDI before TCK TMS before TCK 3 3 A, B, CLK, LE, or OE after TCK 0.5 0.5 TDI after TCK TMS after TCK 0.5 0.5
CLK high 3.5 3.5 CLK low 2 2
CLK high or low 2 2
SN54ABT18504 SN74ABT18504
MIN MAX MIN MAX
7.5 7.5
0.5 0.5
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
27
Page 28
SN54ABT18504, SN74ABT18504
(INPUT)
(OUTPUT)
A or B
B or A
ns
CLKAB or CLKBA
B or A
ns
LEAB or LEBA
B or A
ns
OEAB
OEBA
B or A
ns
OEAB or OEBA
B or A
ns
(INPUT)
(OUTPUT)
TCK
A or B
ns
TCK
TDO
ns
TCK
A or B
ns
TCK
TDO
ns
TCK
A or B
ns
TCK
TDO
ns
SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 13)
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
2 3.8 5.2 2 6.5 2 6 2 3.8 6 2 7.2 2 6.5
2.5 4.7 6.1 2.5 7.2 2.5 6.8
2.5 4.7 6 2.5 7.1 2.5 6.5
2.5 4.9 6.4 2.5 7.5 2.5 7.1
2.5 4.9 6.5 2.5 7.8 2.5 7.2 2 4.9 6.3 2 7.5 2 7
2.5 5.6 7.2 2.5 8.3 2.5 8 3 6.1 7.8 3 9.6 3 8.8
2.5 4.8 6.5 2.5 7.4 2.5 7.3
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM
CLKAB or CLKBA 100 130 100 100 MHz
or
TO
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 13)
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
2.5 9.1 11.5 2.5 14.5 2.5 13.5
2.5 9.1 11 2.5 14 2.5 12.5 2 3.8 5.8 2 7 2 6.5 2 3.8 6 2 7 2 6.5
4.5 9.5 12 4.5 14.5 4.5 13.8 5 10.1 13 5 15 5 14.5
2.5 4.6 6.2 2.5 7.5 2 7 3 5.2 7 3 8 3 7.5 4 11.6 15 4 18 4 17 3 11.1 14.5 3 17.5 3 16 3 5.3 7.6 3 9.5 3 9 3 5.2 6.8 3 8 3 7.5
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
FROM
TCK 50 90 50 50 MHz
TO
SN54ABT18504 SN74ABT18504
SN54ABT18504 SN74ABT18504
UNIT
UNIT
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
28
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Page 29
From Output
Under Test
CL = 50 pF
(see Note A)
Input
PARAMETER MEASUREMENT INFORMATION
500
500
LOAD CIRCUIT FOR OUTPUTS
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
S1
7 V
Open
GND
3 V
0 V
SN54ABT18504, SN74ABT18504
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS108B – AUGUST 1992 – REVISED JUNE 1993
TEST S1
Timing Input
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
Open
1.5 V
t
7 V
h
3 V
0 V
3 V
0 V
Input
(see Note B)
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
INVERTING AND NON-INVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
Figure 13. Load Circuit and Voltage Waveforms
t
PHL
1.5 V
t
PLH
1.5 V1.5 V
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
[
0 V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
29
Page 30
IMPORTANT NOTICE
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Copyright 1998, Texas Instruments Incorporated
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