Datasheet SN74ABT18245ADGGR, SN74ABT18245ADL, SN74ABT18245ADLR Datasheet (Texas Instruments)

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

D

Members of the Texas Instruments

SCOPE

D

Members of the Texas Instruments

Widebus

D

Compatible With the IEEE Standard

 Family of Testability Products

 Family

1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

D

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, CLAMP and HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation

From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Packaged in Plastic Shrink Small-Outline
(DL) and Thin Shrink Small-Outline (DGG)
Packages and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages

description

The ’ABT18245A scan test devices with 18-bit bus
transceivers are members of the Texas
Instruments SCOPE testability integrated­circuit family . This family of devices supports IEEE
Standard 1 149.1-1990 boundary scan to facilitate
testing of complex circuit-board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.

SN54ABT18245A . . . WD PACKAGE

SN74ABT18245A . . . DGG OR DL PACKAGE

1DIR

1B1
1B2

GND

1B3
1B4

V

CC

1B5
1B6
1B7

GND

1B8
1B9
2B1
2B2
2B3
2B4

GND

2B5
2B6
2B7

V

CC

2B8

2B9
GND
2DIR

TDO
TMS

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

1OE
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
1A7
GND
1A8
1A9
2A1
2A2
2A3
2A4
GND
2A5
2A6
2A7
V

CC

2A8
2A9
GND
2OE
TDI
TCK

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot
samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE

) inputs. Data transmission is
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE
be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE bus transceivers is inhibited and the test circuitry is
enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

can

1

SN54ABT18245A, SN74ABT18245A

OPERATION

SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

description (continued)

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data
output (TDO), test-mode select (TMS), and test clock (TCK). Additionally , the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT18245A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(normal mode, each 9-bit section)

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

2

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functional block diagram

1

1DIR

56

1OE

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

Boundary-Scan Register

14

2

1B1

55

1A1

One of Nine Channels

26

2DIR

31

2OE

43

2A1 2B1

One of Nine Channels

Bypass Register

Boundary-Control

Register

TDI

TMS

TCK

30

28

29

Identification

V

CC

V

CC

TAP

Controller

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Register

Instruction Register

27

TDO

3

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

Terminal Functions

TERMINAL

NAME

1A1–1A9,

2A1–2A9

1B1–1B9,

2B1–2B9

1DIR, 2DIR Normal-function direction controls. See function table for normal-mode logic.

GND Ground

1OE, 2OE Normal-function output enables. See function table for normal-mode logic.

TCK

TDI

TDO

TMS
V

CC

Normal-function A-bus I/O ports. See function table for normal-mode logic.

Normal-function B-bus I/O ports. See function table for normal-mode logic.

T est clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

T est data input. One of four terminals required by IEEE Standard 1 149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.

Supply voltage

DESCRIPTION

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard
1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and four test-data registers: a 44-bit boundary-scan register, a
3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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Update-IR

TMS = LTMS = H

5

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

state diagram description

The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.

For the ’ABT18245A, the instruction register is reset to the binary value 10000001, which selects the IDCODE
instruction. Bits 43–40 in the boundary-scan register are reset to logic 0, ensuring that these cells, which control
the A-port and B-port outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at
the high-impedance state). Reset values of other bits in the boundary-scan register should be considered
indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test
operation.

Run-Test/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic actively can be running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the T AP controller exits the Capture-DR
state.

6

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SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first
falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level
present in the least significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such updates occur
on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the ’ABT18245A, the
status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On
the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the
logic level present in the least significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of
data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR
state.

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7

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the ’ABT18245A. The even-parity feature specified for SCOPE
devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are
defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 7
Parity
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

TDOTDI

Figure 2. Instruction Register Order of Scan

8

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SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

data register description

boundary-scan register

The boundary-scan register (BSR) is 44 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin, one BSC for each normal-function I/O pin (one single cell for both input data and
output data), and one BSC for each of the internally decoded output-enable signals (1OEA, 2OEA, 1OEB,
2OEB). The BSR is used to store test data that is to be applied externally to the device output pins, and/or to
capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device
input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up
or in Test-Logic-Reset, BSCs 43–40 are reset to logic 0, ensuring that these cells, which control A-port and
B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the
high-impedance state). Reset values of other BSCs should be considered indeterminate.

When external data is to be captured, the BSCs for signals 1OEA, 2OEA, 1OEB, and 2OEB capture logic values
determined by the following positive-logic equations: 1OEA = 1OE
1OEB = 1OE

• DIR, and 2OEB = 2OE • DIR. When data is to be applied externally, these BSCs control the

drive state (active or high impedance) of their respective outputs.

• 1DIR, 2OEA = 2OE • 2DIR,

The BSR order of scan is from TDI through bits 43–0 to TDO. T able 1 shows the BSR bits and their associated
device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

43 2OEB 35 2A9-I/O 26 1A9-I/O 17 2B9-I/O 8 1B9-I/O
42 1OEB 34 2A8-I/O 25 1A8-I/O 16 2B8-I/O 7 1B8-I/O
41 2OEA 33 2A7-I/O 24 1A7-I/O 15 2B7-I/O 6 1B7-I/O
40 1OEA 32 2A6-I/O 23 1A6-I/O 14 2B6-I/O 5 1B6-I/O
39 2DIR 31 2A5-I/O 22 1A5-I/O 13 2B5-I/O 4 1B5-I/O
38 1DIR 30 2A4-I/O 21 1A4-I/O 12 2B4-I/O 3 1B4-I/O
37 2OE 29 2A3-I/O 20 1A3-I/O 11 2B3-I/O 2 1B3-I/O
36 1OE 28 2A2-I/O 19 1A2-I/O 10 2B2-I/O 1 1B2-I/O
  27 2A1-I/O 18 1A1-I/O 9 2B1-I/O 0 1B1-I/O

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test
(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.
Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that
are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in
Figure 3.

DEVICE

SIGNAL

Bit 2

(MSB)

Bit 1

Bit 0

(LSB)

Figure 3. Boundary-Control Register Order of Scan

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TDOTDI

9

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in
Figure 4.

Bit 0

TDOTDI

Figure 4. Bypass Register Order of Scan

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.

During Capture-DR, the binary value 00010000000000000101000000101111 (1000502F, hex) is captured in
the IDR to identify this device as Texas Instruments SN54/74ABT18245A. The IDR order of scan is from TDI
through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

31 VERSION3 27 PARTNUMBER15 11 MANUFACTURER10
30 VERSION2 26 PARTNUMBER14 10 MANUFACTURER09
29 VERSION1 25 PARTNUMBER13 9 MANUFACTURER08
28 VERSION0 24 PARTNUMBER12 8 MANUFACTURER07

  23 P ARTNUMBER11 7 MANUFACTURER06
  22 PARTNUMBER10 6 MANUFACTURER05
  21 PARTNUMBER09 5 MANUFACTURER04
  20 PARTNUMBER08 4 MANUFACTURER03
  19 PARTNUMBER07 3 MANUFACTURER02
  18 PARTNUMBER06 2 MANUFACTURER01
  17 PARTNUMBER05 1 MANUFACTURER00
  16 PARTNUMBER04 0 LOGIC1
  15 PARTNUMBER03  
  14 PARTNUMBER02  
  13 PARTNUMBER01  
  12 PARTNUMBER00  

†

Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111
(02F, hex).

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

†

†
†
†
†
†
†
†
†
†
†
†

10

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SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each
instruction.

Table 3. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

00000000 EXTEST Boundary scan Boundary scan Test
10000001 IDCODE Identification read Device identification Normal
10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal
0000001 1 BYPASS
10000100 BYPASS
00000101 BYPASS
00000110 HIGHZ Control boundary to high impedance Bypass Modified test
100001 11 CLAMP Control boundary to 1/0 Bypass Test
10001000 BYPASS
00001001 RUNT Boundary-run test Bypass Test
00001010 READBN Boundary read Boundary scan Normal
1000101 1 READBT Boundary read Boundary scan Test
00001 100 CELLTST Boundary self test Boundary scan Normal
10001 101 TOPHIP Boundary toggle outputs Bypass Test
10001 110 SCANCN Boundary-control register scan Boundary control Normal
00001 111 SCANCT Boundary-control register scan Boundary control Test
All others BYP ASS Bypass scan Bypass Normal

†

Bit 7 is used to maintain even parity in the 8-bit instruction.

‡

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’ABT18245A.

†

SCOPE OPCODE DESCRIPTION

‡
‡
‡

‡

SELECTED DATA

REGISTER

Bypass scan Bypass Normal
Bypass scan Bypass Normal
Bypass scan Bypass Normal

Bypass scan Bypass Normal

MODE

boundary scan

This instruction conforms to the IEEE Standard 1 149.1-1990 EXTEST instruction. The BSR is selected in the
scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has
been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into
the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device I/O pins
is passed through the I/O BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output
is determined by the contents of the output-enable BSCs (bits 43–40 of the BSR). When a given output enable
is active (logic 1), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the
input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the
scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured
in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs
associated with I/O pins in the output mode. The device operates in the normal mode.

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11

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the I/O BSCs for pins in the output mode
is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way , the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising
edge of TCK in Run-T est/Idle, updated in the shadow latches, and applied to the associated device I/O pins on
each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at
the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to be
executed.

12

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SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2–0 as shown in T able 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-T est/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

X00 Sample inputs/toggle outputs (TOPSIP)
X01 Pseudo-random pattern generation/36-bit mode (PRPG)
X10 Parallel-signature analysis/36-bit mode (PSA)

011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 43–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 43–40 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when both bytes of the device are operating in one
direction of data flow (i.e., 1OEA ≠ 1OEB and 2OEA ≠ 2OEB) and in the same direction of data flow
(i.e.,1OEA = 2OEA and 1OEB = 2OEB). Otherwise, the bypass instruction is operated.

DESCRIPTION

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.

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SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each
falling edge of TCK. Figures 5 and 6 illustrate the 36-bit linear-feedback shift-register algorithms through which
the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

=

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 5. 36-Bit PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

14

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pseudo-random pattern generation (PRPG) (continued)

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

=

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 6. 36-Bit PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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15

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the
selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8
illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

=

=

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 7. 36-Bit PSA Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

16

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parallel-signature analysis (PSA) (continued)

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

=

=

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 8. 36-Bit PSA Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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17

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in
the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an
18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each
falling edge of TCK. Figures 9 and 10 illustrate the 18-bit linear-feedback shift-register algorithms through which
the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

=

=

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

18

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simultaneous PSA and PRPG (PSA/PRPG) (continued)

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O1B9-I/O

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

=

=

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

Figure 10. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

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SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in
the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an
18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on
each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each
falling edge of TCK. Figures 11 and 12 illustrate the 18-bit linear-feedback shift-register algorithms through
which the signature is generated. An initial seed value should be scanned into the BSR before performing this
operation.

2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A8-I/O2A9-I/O

1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A8-I/O1A9-I/O

MSB

2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B9-I/O

=

=

1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B9-I/O

Figure 11. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1)

LSB

20

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simultaneous PSA and binary count up (PSA/COUNT) (continued)

2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O2B8-I/O2B9-I/O

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

1B9-I/O

MSB

2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O2A9-I/O

=

=

1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O1A9-I/O

1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O1B8-I/O

Figure 12. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0)

LSB

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21

SN54ABT18245A, SN74ABT18245A
SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

timing description

All test operations of the ’ABT18245A are synchronous to TCK. Data on the TDI, TMS, and normal-function
inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the
falling edge of TCK. The T AP controller is advanced through its states (as shown in Figure 1) by changing the
value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register
scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and
TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5
details the operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

1 Test-Logic-Reset
2 Run-Test/Idle

3 Select-DR-Scan
4 Select-IR-Scan

5 Capture-IR

6 Shift-IR

7–13 Shift-IR

14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
16 Select-DR-Scan

17 Capture-DR

18 Shift-DR

19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22 Update-DR The selected data register is updated with the new data on the falling edge of TCK.
23 Select-DR-Scan
24 Select-IR-Scan
25 Test-Logic-Reset Test operation completed

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next
TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ООООО

ООООО

TCK

TMS

TDO

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TDI

TAP

Controller

State

Run-Test/Idle

Test-Logic-Reset

Select-DR-Scan

Capture-IR

Select-IR-Scan

Shift-IR

3-State (TDO) or Don’t Care (TDI)

Exit1-IR

Update-IR

Capture-DR

Select-DR-Scan

Shift-DR

Exit1-DR

Update-DR

Select-IR-Scan

Select-DR-Scan

Figure 13. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Input voltage range, V
Voltage range applied to any output in the high state or power-off state, V
Current into any output in the low state, I

Input clamp current, I
Output clamp current, I
Continuous current through V

Continuous current through GND 1152 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(I/O ports) (see Note 1) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

: SN54ABT18245A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.5 V to 5.5 V. . . . . . . . . . . . . .

O

SN74ABT18245A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

576 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Test-Logic-Reset

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

SN54ABT18245A, SN74ABT18245A

UNIT

SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

recommended operating conditions (see Note 3)

SN54ABT18245A SN74ABT18245A

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 10 10 ns/V
T

A

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

CC

0 V

CC

V

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

I

CC

,

A

V

CC

A or

∆I

¶

CC

,,

505050µA

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT18245A SN74ABT18245A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

OL

I

I

IH

I

IL

I

OZH

I

OZL

I

OZPU

I

OZPD

I

off

I

CEX

§

I

O

I

CC

CC

C

i

C

io

C

o

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

The parameters I

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
VCC = 4.5 V, IOH = –24 mA 2 2
VCC = 4.5 V, IOH = –32 mA 2* 2

= 4.5

CC

V

= 5.5 V,

VI = VCC or GND
VCC = 5.5 V,

VI = V

CC

VCC = 5.5 V,
VI = GND

‡

VCC = 5.5 V, VO = 2.7 V 50 50 50 µA

‡

VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
VCC = 0 to 2 V,

VO = 2.7 V or 0.5 V
VCC = 2 V to 0,

VO = 2.7 V or 0.5 V
VCC = 0, VI or VO ≤ 4.5 V ±100 ±450 ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –110 –200 –50 –200 –50 –200 mA

=

= 5.5 V,
IO = 0,
VI = VCC or GND ports

V

= 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V Control inputs 3 9.8 pF
VO = 2.5 V or 0.5 V A or B ports 10 12.6 pF
VO = 2.5 V or 0.5 V TDO 8 11.4 pF

and I

OZH

OZL

IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

DIR, OE, TCK ±1 ±1 ±1
A or B ports ±100 ±100 ±100

TDI, TMS 10 10 10 µA

TDI, TMS –40 –150 –40 –150 –40 –150 µA

OE = 0.8 V

OE = 0.8 V

Outputs high 50 50 50 µA

Outputs high 3.5 5 5 5
Outputs low 33 38 38 38

B

Outputs disabled 2.9 4.5 4.5 4.5

include the input leakage current.

±50 ±50 ±50 µA

±50 ±50 ±50 µA

µ

mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

SN54ABT18245A, SN74ABT18245A

UNIT

(INPUT)

(OUTPUT)

A or B

B or A

ns

OE

B or A

ns

OE

B or A

ns

(INPUT)

(OUTPUT)

TCK↓

A or B

ns

TCK↓

TDO

ns

TCK↓

A or B

ns

TCK↓

TDO

ns

TCK↓

A or B

ns

TCK↓

TDO

ns

SCAN TEST DEVICES
WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)

SN54ABT18245A SN74ABT18245A

MIN MAX MIN MAX

f

clock

t

w

t

su

t

h

t

d

t

r

* On products compliant to MIL-PRF-38535, these parameters are not production tested.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 14)

Clock frequency TCK 0 50 0 50 MHz
Pulse duration TCK high or low 8.1 8.1 ns

A, B, DIR, or OE before TCK↑ 9.5 7

Setup time

Hold time

Delay time Power up to TCK↑ 50* 50 ns
Rise time VCC power up 1* 1 µs

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

FROM

TDI before TCK↑
TMS before TCK↑ 3.6 3.6
A, B, DIR, or OE after TCK↑ 0.7 0
TDI after TCK↑
TMS after TCK↑ 0.5 0.5

TO

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

1.5 2.8 4.1 1.5 5.1 1.5 4.8

1.5 3.1 4.6 1.5 5.8 1.5 5.4
2 4.7 5.8 2 8.1 2 7.5
2 4.5 6.2 2 8.5 2 8

2.5 5.8 6.8 2.5 9.5 2.5 8.5

2.5 4.8 6 2.5 8.5 2.5 7.5

4.5 4.5

0 0

SN54ABT18245A SN74ABT18245A

ns

ns

UNIT

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 14)

PARAMETER

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PHZ

t

PLZ

FROM

TCK↓ 50 90 50 50 MHz

TO

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

3 7.1 10.1 2.8 14 3 13.1
3 7 10.1 3 13.8 3 12.8
2 3.4 5 2 6.4 2 6.1
2 3.9 5.6 2 7 2 6.5
4 7.5 10.6 4 14.1 4 13.4
4 7.6 10.5 4 14.3 4 13.6
2 3.8 5.5 2 7 2 6.6

2.5 4 5.7 2.3 7.3 2.5 6.9

3.5 7.7 10.8 2.9 14.4 3.5 13.6

2.5 7.1 10.1 2.5 13.8 2.5 12.7
2 3.9 5.7 2 7.5 2 7.2

1.5 3.5 5.4 1.5 6.7 1.5 6.3

SN54ABT18245A SN74ABT18245A

UNIT

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT18245A, SN74ABT18245A

SCAN TEST DEVICES

WITH 18-BIT BUS TRANSCEIVERS

SCBS110H – AUGUST 1992 – REVISED FEBRUAR Y 1999

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Open

Open

1.5 V

t

7 V

h

1.5 V

VOL + 0.3 V

VOH – 0.3 V

1.5 V

t

PLZ

t

PHZ

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

V

[

OL

OH

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

27

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