Page 1
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54ABT16841 . . . WD PACKAGE
SN74ABT16841 . . . DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2LE
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE
or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critic al applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16841 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
EN2
C1
EN4
C3
1D
3D
2
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
2
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
UNIT
logic diagram (positive logic)
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
1OE
1LE
1D1
1
56
55
C1
1D
To Nine Other Channels
2
1Q1
2OE
2LE
2D1
28
29
42
C1
1D
To Nine Other Channels
15
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16841 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
SN74ABT16841 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
SN54ABT16841 SN74ABT16841
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54ABT16841, SN74ABT16841
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
A
V
I
V
CC
GND
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16841 SN74ABT16841
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
‡
I
OZPU
‡
I
OZPD
I
OZH
I
OZL
I
off
I
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
CEX
§
I
O
Outputs high
I
Outputs low
CC
Outputs disabled
¶
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1
VCC = 5 V, VI = VCC or GND ±5
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
or
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 7.5 pF
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
= X
= X
≥ 2 V
≥ 2 V
±50 ±50 ±50 µA
±50 ±50 ±50 µA
10 10 10 µA
–10 –10 –10 µA
0.5 0.5
89 89 89
0.5 0.5 0.5
1.5 1.5 1.5 mA
µ
mA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16841
4
t
w
t
su
t
h
VCC = 5 V,
TA = 25°C
MIN MAX
Pulse duration, LE high or low 4 4 ns
Setup time, data before LE↓ 3 3 ns
Hold time, data after LE↓ 2.6 2.6 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN MAX
UNIT
Page 5
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT16841
VCC = 5 V,
TA = 25°C
MIN MAX
t
w
t
su
t
h
Pulse duration, LE high or low 4 4 ns
Setup time, data before LE↓ 1 1 ns
Hold time, data after LE↓ 2 2 ns
MIN MAX
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
SN54ABT16841
VCC = 5 V,
TA = 25°C
MIN TYP MAX
1.1 3.2 4.3 1.1 5.7
1.6 3.5 4.5 1.6 5.3
1.1 3.2 4.4 1.1 5.6
1.6 3.4 5 1.6 5.5
1.2 3.2 4.7 1.2 5.8
1.7 3.6 5 1.7 5.7
2.2 4.1 6.6 2.2 7.7
1.9 4.4 5.8 1.2 8.4
MIN MAX
UNIT
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
TO
(OUTPUT)
SN74ABT16841
VCC = 5 V,
TA = 25°C
MIN TYP MAX
1.1 3.2 4.3 1.1 5
1.6 3.5 4.5 1.6 5.1
1.1 3.2 4.4 1.1 5
1.6 3.4 4.6 1.6 5
1.2 3.2 4.7 1.2 5.7
1.7 3.6 5 1.7 5.6
2.2 4.1 5.7 2.2 6.5
1.9 4.4 5.8 1.9 7.1
MIN MAX
UNIT
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5
Page 6
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
1.5 V1.5 V
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
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