Page 1
SN54ABT16827, SN74ABT16827
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS220C – JUNE 1992 – REVISED MA Y 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
The ’ABT16827 are noninverting 20-bit buffers
composed of two 10-bit sections with separate
output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1
or 2OE1 and 2OE2) inputs must both be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer section are in the high-impedance
state.
and 1OE2
SN54ABT16827 . . . WD PACKAGE
SN74ABT16827 . . . DL PACKAGE
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16827 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16827 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN54ABT16827, SN74ABT16827
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS220C – JUNE 1992 – REVISED MA Y 1997
FUNCTION TABLE
(each 10-bit section)
INPUTS
OE1 OE2 A
L L L L
L LH H
H XX Z
X H X Z
OUTPUT
Y
logic symbol
†
1OE1
1OE2
2OE1
2OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
&
&
11
12
EN1
EN2
10
12
13
14
15
16
17
19
20
21
23
24
26
27
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
1Y5
9
1Y6
1Y7
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
2Y9
2Y10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
UNIT
∆t/∆vInput transition rise or fall rate
ns/V
logic diagram (positive logic)
SN54ABT16827, SN74ABT16827
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS220C – JUNE 1992 – REVISED MA Y 1997
1OE1
1OE2
1A1
1
56
55
2
1Y1
To Nine Other Channels To Nine Other Channels
2OE1
2OE2
2A1
28
29
42
15
2Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16827 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
SN74ABT16827 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions (see Note 3)
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
p
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Control pins 4 4
Data pins 10 10
SN54ABT16827 SN74ABT16827
MIN MAX MIN MAX
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54ABT16827, SN74ABT16827
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
V
I
V
CC
GND
(INPUT)
(OUTPUT)
A
Y
ns
OE
Y
ns
OE
Y
ns
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS220C – JUNE 1992 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16827 SN74ABT16827
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
I
‡
I
OZPU
‡
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized, but not production tested.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
§
Outputs high
Outputs low
Outputs disabled
¶
CC
i
o
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 5.5 V,
VI = VCC or GND
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 7.5 pF
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
±1 ±1 ±1 µA
= X
= X
≥ 2 V
≥ 2 V
or
±50 ±50 ±50 µA
±50 ±50 ±50 µA
10 10 10 µA
–10 –10 –10 µA
2 2 2
32 32 32
2 2 2
1.5 1.5 1.5 mA
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
TO
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
1 1.9 3.1 1 3.6 1 3.4
1 2.1 3.7 1 4.5 1 4.2
1 2.8 5 1 5.9 1 5.6
1 2.8 4.9 1 5.8 1 5.5
2.4 4.5 6.5 2.4 6.8 2.4 6.6
1.6 3.7 5.7 1.6 7.1 1.6 6.1
SN54ABT16827 SN74ABT16827
UNIT
Page 5
From Output
Under Test
Input
CL = 50 pF
(see Note A)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
500 Ω
LOAD CIRCUIT
t
w
SN54ABT16827, SN74ABT16827
20-BIT BUFFERS/DRIVERS
SCBS220C – JUNE 1992 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
7 V
500 Ω
S1
Open
GND
3 V
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
WITH 3-STATE OUTPUTS
Open
7 V
Open
3 V
1.5 V
0 V
t
su
h
3 V
0 V
Input
t
PLH
Output
t
PHL
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.5 V1.5 V
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
t
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...