Datasheet SN74ABT16823DGGR, SN74ABT16823DL, SN74ABT16823DLR, SNJ54ABT16823WD Datasheet (Texas Instruments)
Page 1
SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
High-Impedance State During Power Up
and Power Down
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes
PCB Layout
D
High-Drive Outputs (–32-mA IOH,
64-mA IOL)
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
SN54ABT16823 . . . WD PACKAGE
SN74ABT16823 . . . DGG OR DL PACKAGE
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
The ’ABT16823 can be used as two 9-bit flip-flops
or one 18-bit flip-flop. With the clock-enable
(CLKEN
) input low, the D-type flip-flops enter data
on the low-to-high transitions of the clock. Taking
CLKEN
high disables the clock buffer , latching the
outputs. Taking the clear (CLR) input low causes
the Q outputs to go low independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
The SN54ABT16823 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16823 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
OE
CLR CLKEN
L L X X X L
L HL↑ HH
L HL↑ LL
L HLLX Q
L HHXX Q
H X X X X Z
CLK D
OUTPUT
Q
0
0
2
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Page 3
SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
logic symbol
†
2
1OE
1CLR
1CLKEN
1CLK
2CLR
2CLKEN
2CLK
1
55
56
27
2OE
28
30
29
54
1D1 1Q1
52
1D2 1Q2
51
1D3
49
1D4
48
1D5
47
1D6
45
1D7 1Q7
44
1D8 1Q8
43
1D9 1Q9
42
2D1 2Q1
41
2D2 2Q2
40
2D3 2Q3
38
2D4 2Q4
37
2D5 2Q5
36
2D6 2Q6
34
2D7 2Q7
33
2D8
31
2D9
EN1
R2
G3
EN5
R6
G7
4D
8D
3C4
7C8
1, 2
5, 6
10
12
13
14
15
16
17
19
20
21
23
24
26
3
5
6
1Q3
8
1Q4
9
1Q5
1Q6
2Q8
2Q9
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
logic diagram (positive logic)
2
1OE
1CLR
1CLKEN
1CLK
2OE
2CLR
2CLKEN
2CLK
1
55
56
27
28
30
29
1D1
2D1
54
42
CE
R
C1
1D
To Eight Other Channels
CE
R
C1
1D
15
3
1Q1
2Q1
To Eight Other Channels
4
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Page 5
UNIT
SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT16823 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
SN74ABT16823 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16823 SN74ABT16823
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
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Page 6
SN54ABT16823, SN74ABT16823
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
V
I
V
CC
GND
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16823 SN74ABT16823
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
I
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABT16823.
†
All typical values are at VCC = 5 V.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA
‡
Outputs high
Outputs low
Outputs disabled
§
CC
i
o
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 0 to 5.5 V,
VI = VCC or GND
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
VCC = 5.5 V, IO = 0,
=
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 7.5 pF
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
±1 ±1 ±1 µA
= X
= X
≥ 2 V
≥ 2 V
or
±50 ±50 ±50 µA
±50 ±50 ±50 µA
**
10
**
–10
0.5 0.5 0.5
80 80 80
0.5 0.5 0.5
1.5 1.5 1.5 mA
50 10 µA
–50 –10 µA
mA
6
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Page 7
twPulse duration
ns
↑
thHold time after CLK↑
ns
CLK
Q
ns
OE
Q
ns
OE
Q
ns
CLK
Q
ns
OE
Q
ns
OE
Q
ns
SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
f
clock
t
su
Clock frequency 0 150 0 150 0 150 MHz
CLR low 3.3 3.3 3.3
CLK high or low 3.3 3.3 3.3
CLR inactive 1.6 2 1.6
Setup time before CLK
Data 1.7 1.7 1.7
CLKEN low 2.8 2.8 2.8
Data 1.2 1.2 1.2
CLKEN low 0.6 0.6 0.6
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
CLR
TO
(OUTPUT)
Q 1.9 4.1 5.3 1.9 6.3 ns
SN54ABT16823 SN74ABT16823
SN54ABT16823
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 150 MHz
1.6 3.9 5.5 1.6 7.7
2.1 3.9 5.4 2.1 6.4
1 3.1 4.2 1 5.1
1.5 3.5 4.6 1.5 5.7
2.2 4.3 6 2.2 6.8
1.6 4.3 6.4 1.6 9.9
MIN MAX
UNIT
ns
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
CLR
TO
(OUTPUT)
Q 1.9 4.1 5.3 1.9 6.1 ns
SN74ABT16823
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 150 MHz
1.6 3.9 5.5 1.6 6.8
2.1 3.9 5.4 2.1 6
1 3.1 4.2 1 4.9
1.5 3.5 4.6 1.5 5.5
2.2 4.3 5.6 2.2 6.1
1.6 4.3 6.4 1.6 8.7
MIN MAX
UNIT
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SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
S1
7 V
Open
GND
3 V
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
Open
1.5 V
t
7 V
h
3 V
0 V
3 V
0 V
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
8
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Page 9
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