Datasheet SN74ABT16646DGGR, SN74ABT16646DL, SN74ABT16646DLR, SNJ54ABT16646WD Datasheet (Texas Instruments)
Page 1
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
D
Members of the Texas Instruments
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABT16646 devices consist of
bus-transceiver circuits, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’ABT16646 devices.
SN54ABT16646 . . . WD PACKAGE
SN74ABT16646 . . . DGG OR DL PACKAGE
1CLKAB
2CLKAB
1DIR
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2DIR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE
) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the
other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
Page 2
SN54ABT16646, SN74ABT16646
OPERATION OR FUNCTION
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
description (continued)
The SN54ABT16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
X X ↑ X X X Input Unspecified Store A, B unspecified
X XX ↑ X X Unspecified Input Store B, A unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B Bus
L H H or L X H X Input Output Stored A data to bus
†
The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the
bus terminals is stored on every low-to-high transition of the clock inputs.
DATA I/O
†
{
{
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
BUS A
DIRLCLKABXCLKBAXSABXSBA
OE
L
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
L
OE
L
BUS A
DIRHCLKABXCLKBAXSABLSBA
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
X
BUS A
DIRXCLKAB CLKBAXSABXSBA
X
X
H
X
X
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
BUS B
OEOE
X
X
X
X
BUS A
DIRLCLKABXCLKBA
L
L H H or L X H X
TRANSFER STORED DA TA
Figure 1. Bus-Management Functions
H or L
TO A AND/OR B
BUS B
SABXSBA
H
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
logic symbol
†
56
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1
55
54
2
3
29
28
30
31
27
26
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
1DIR
1CLKBA
1SBA
1CLKAB C6
1SAB
2DIR
2CLKBA
2SBA
2CLKAB C13
2SAB
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
G14
≥1
1
6D
177
≥1
8
13D
11414
≥1
≥1
155
11D
11212
4D
2
9
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
logic diagram (positive logic)
56
1OE
1
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
55
54
2
3
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
1A1
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
One of Eight Channels
5
1D
C1
29
28
30
31
27
26
To Seven Other Channels
C1
1D
52
1B1
2A1
15
One of Eight Channels
1D
C1
To Seven Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C1
1D
42
2B1
5
Page 6
SN54ABT16646, SN74ABT16646
UNIT
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
Current into any output in the low state, IO: SN54ABT16646 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT16646 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT16646 SN74ABT16646
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
0 V
CC
V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
VOLV
4.5 V
V
µ
I
CC
,
ICC
µ
V
CC
¶
Data inputs
,
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT16646 SN74ABT16646
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
Control
I
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
inputs
A or B ports
‡
‡
§
A or B ports
p
CC
Control
inputs
Control
i
inputs
A or B ports VO = 2.5 V or 0.5 V 8 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
= 4.5
CC
=
CC
V
= 5.5 V, V
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 4 pF
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
= V
or GND
Outputs high 50 50 50 µA
Outputs high 2 2 2
Outputs low 32 32 32
Outputs disabled 2 2 2
Outputs enabled 50 50 50
Outputs disabled 50 50 50
±1 ±1 ±1
±20 ±20 ±20
50 50 50
A
mA
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16646
VCC = 5 V,
f
clock
t
w
t
su
t
h
TA = 25°C
MIN MAX
Clock frequency 125 125 MHz
Pulse duration, CLK high or low 4.3 4.3 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3.5 4 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 0.5 0.5 ns
MIN MAX
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16646
VCC = 5 V,
f
clock
t
w
t
su
t
h
TA = 25°C
MIN MAX
Clock frequency 125 125 MHz
Pulse duration, CLK high or low 4.3 4.3 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 ns
MIN MAX
UNIT
UNIT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
CLKBA or CLKAB
A or B
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OE
A or B
ns
OE
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
CLKBA or CLKAB
A or B
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OE
A or B
ns
OE
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN54ABT16646
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
1.5 3.1 4 1 5
1.5 3.2 4.1 1 5
1 2.3 3.2 0.6 4
1 3 4.1 0.6 4.9
1 2.9 4.3 0.6 5.3
1 3.1 4.3 0.6 5.3
1 3.4 4.6 0.6 5.9
1.5 3.5 5.3 1 6
1.5 3.9 5.6 1 6.4
1.5 3.1 4.4 1 4.7
1 3.2 4.5 0.6 5.8
1.5 3.4 5.1 1 6.7
2 4.2 5.9 1.2 7.1
1.5 3.6 5.1 1 6.2
MIN MAX
UNIT
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN74ABT16646
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
1.5 3.1 4 1.5 4.9
1.5 3.2 4.1 1.5 4.7
1 2.3 3.2 1 3.9
1 3 4.1 1 4.6
1 2.9 4.3 1 5
1 3.1 4.3 1 5
1 3.4 4.6 1 5.5
1.5 3.5 4.9 1.5 5.7
1.5 3.9 4.9 1.5 5.4
1.5 3.1 4.1 1.5 4.5
1 3.2 4.5 1 5.4
1.5 3.4 4.8 1.5 5.6
2 4.2 5.7 2 6.7
1.5 3.6 5.1 1.5 5.9
MIN MAX
UNIT
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9
Page 10
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JUL Y 1999
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
GND
OH
OL
OH
OL
Open
3 V
0 V
Timing Input
Data Input
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
10
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 11
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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