Datasheet SN74ABT16541ADGGR, SN74ABT16541ADGVR, SN74ABT16541ADL, SN74ABT16541ADLR Datasheet (Texas Instruments)

SN54ABT16541, SN74ABT16541A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS118C – FEBRUAR Y 1991 – REVISED JANUAR Y 1997

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

Typical V

(Output Ground Bounce)

OLP

< 0.8 V at VCC = 5 V, TA = 25°C

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Spacings

description

The SN54ABT16541 and SN74ABT16541A are
noninverting 16-bit buffers composed of two 8-bit
sections with separate output-enable signals. For
either 8-bit buffer section, the two output-enable
(1OE1

and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 8-bit buffer section are in the
high-impedance state.

SN74ABT16541A . . . DGG, DGV, OR DL PACKAGE

SN54ABT16541 . . . WD PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE2
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V

CC

2A5
2A6
GND
2A7
2A8
2OE2

1OE1

1Y1
1Y2

GND

1Y3
1Y4

V

CC

1Y5
1Y6

GND

1Y7
1Y8
2Y1
2Y2

GND

2Y3
2Y4

V

CC

2Y5
2Y6

GND

2Y7
2Y8

2OE1

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16541 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16541A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit section)

INPUTS

OE1 OE2

L L L L

L LH H
H XX Z
X H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUTPUT

A

Y

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT16541, SN74ABT16541A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS118C – FEBRUAR Y 1991 – REVISED JANUAR Y 1997

logic symbol

†

1OE1
1OE2
2OE1

2OE2

1
48

24
25

47

1A1

46

1A2

44

1A3 1Y3

43

1A4 1Y4

41

1A5 1Y5

40

1A6 1Y6

38

1A7 1Y7

37

1A8 1Y8

36

2A1 2Y1

35

2A2

33

2A3 2Y3

32

2A4 2Y4

30

2A5 2Y5

29

2A6 2Y6

27

2A7

26

2A8

&

&

EN1

EN2

111

2

1Y1

3

1Y2

5
6
8

9
11
12

2

13
14
16
17
19
20
22
23

2Y2

2Y7
2Y8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1

1OE1

48

1OE2

47

1A1 1Y1

To Seven Other Channels To Seven Other Channels

2

2OE1
2OE2

2A1

24
25

36

13

2Y1

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54ABT16541, SN74ABT16541A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS118C – FEBRUAR Y 1991 – REVISED JANUAR Y 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT16541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

SN74ABT16541A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ABT16541 SN74ABT16541A

MIN MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

CC

0 V

CC

V

†

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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3

SN54ABT16541, SN74ABT16541A

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

VOLV

V

V

V

CC

§

,

(INPUT)

(OUTPUT)

A

Y

ns

OE

Y

ns

OE

Y

ns

16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS118C – FEBRUAR Y 1991 – REVISED JANUAR Y 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT16541 SN74ABT16541A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

V

hys

I

I

I

OZH

I

OZL

I

off

I

CEX

‡

I

O

I

CC

Data

∆I

C
C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

inputs

CC

Control
inputs

i
o

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10 50 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –50 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

=

= 5.5 V,
IO = 0,
VI = VCC or GND

VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 3.5 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

Outputs high 50 50 50 µA

Outputs high 3 2 3
Outputs low 34 32 34
Outputs disabled 3 2 3

Outputs enabled 1 1.5 1

Outputs disabled 0.05 0.05 0.05

1.5 1.5 1.5

mA

mA

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

TO

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VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

1 2.1 3 1 3.5 1 3.4
1 2.5 3.6 1 4.3 1 4.2

1.3 3.2 4.3 1.3 5.3 1.3 5.2

1.6 3.8 4.7 1.6 6.2 1.6 6

1.3 4.1 4.8 1.3 5.4 1.3 5.4
1 3.3 4 1 4.3 1 4.3

SN54ABT16541 SN74ABT16541A

UNIT

SN54ABT16541, SN74ABT16541A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS118C – FEBRUAR Y 1991 – REVISED JANUAR Y 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

1.5 V1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

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5

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