Datasheet SN74ABT162841DGGR, SN74ABT162841DL, SN74ABT162841DLR Datasheet (Texas Instruments)

SN54ABT162841, SN74ABT162841

20-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

These 20-bit transparent D-type latches feature
noninverting 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.

The ’ABT162841 can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE

or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.

The outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.

OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critic al applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

SN54ABT162841 . . . WD PACKAGE

SN74ABT162841 . . . DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1OE

1Q1
1Q2

GND

1Q3
1Q4

V

CC

1Q5
1Q6
1Q7

GND

1Q8
1Q9

1Q10

2Q1
2Q2
2Q3

GND

2Q4
2Q5
2Q6

V

CC

2Q7
2Q8

GND

2Q9

2Q10

2OE

1LE
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V

CC

2D7
2D8
GND
2D9
2D10
2LE

SN54ABT162841, SN74ABT162841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT162841 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162841 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 10-bit latch)

INPUTS

OUTPUT

OE LE D

Q

L H H H
L HL L
L LX Q

0

H X X Z

SN54ABT162841, SN74ABT162841

20-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1Q1

2

1Q2

3

1Q3

5

1Q4

6

1Q5

8

1D

55

1D1

54

1D2

52

1D3

51

1D4

49

1D5

48

1D6

47

1D7

45

1D8

44

1D9

43

1D10

1Q6

9

1Q7

10

1Q8

12

1Q9

13

1Q10

14

3D

42

2D1

41

2D2

40

2D3

38

2D4

37

2D5

2Q1

15

2Q2

16

2Q3

17

2Q4

19

2Q5

20

36

2D6

34

2D7

33

2D8

31

2D9

30

2D10

2Q6

21

2Q7

23

2Q8

24

2Q9

26

2Q10

27

EN2

1

C1

56

1LE

EN4

28

C3

29

2LE

1OE

2OE

2

4

logic diagram (positive logic)

1OE

To Nine Other Channels

1

56

55

2

1LE

1D1

C1
1D

1Q1

2OE

To Nine Other Channels

28

29

42

15

2LE

2D1

C1
1D

2Q1

SN54ABT162841, SN74ABT162841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DGG package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

recommended operating conditions (see Note 3)

SN54ABT162841 SN74ABT162841

MIN MAX MIN MAX

UNIT

V

CC

Supply voltage 4.5 5.5 4.5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.8 0.8 V

V

I

Input voltage 0 V

CC

0 V

CC

V

I

OH

High-level output current –12 –12 mA

I

OL

Low-level output current 12 12 mA

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V

CC

Power-up ramp rate 200 200 µs/V

T

A

Operating free-air temperature –55 125 –40 85 °C

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ABT162841, SN74ABT162841

20-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT162841 SN74ABT162841

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN MAX MIN MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –1 mA 3 3 3

V

OH

IOH = –3 mA 2.4 2.4 2.4

V

V

CC

=

4.5 V

IOH = –12 mA 2* 2
IOL = 8 mA 0.4 0.8 0.8 0.65

VOLV

CC

= 4.5

V

IOL = 12 mA 0.55* 0.8

V

V

hys

100 mV

I

I

VCC = 0 to 5.5 V,
VI = VCC or GND

±1 ±1 ±1 µA

I

OZPU

‡

VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE

= X

±50 ±50 ±50 µA

I

OZPD

‡

VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE

= X

±50 ±50 ±50 µA

I

OZH

VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE

≥ 2 V

10 10 10 µA

I

OZL

VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE

≥ 2 V

–10 –10 –10 µA

I

off

VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA

I

CEX

Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 50 µA

I

O

§

VCC = 5.5 V, VO = 2.5 V –25 –75 –100 –25 –100 –25 –100 mA

Outputs high

0.5 0.5 0.5

I

CC

Outputs low

VCC = 5.5 V, IO = 0,

89 89 89

mA

Outputs disabled

V

I

=

V

CC

or

GND

0.5 0.5 0.5

∆I

CC

¶

VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND

1.5 1.5 1.5 mA

C

i

VI = 2.5 V or 0.5 V 3.5 pF

C

o

VO = 2.5 V or 0.5 V 9 pF

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

This parameter is characterized, but not production tested.

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

VCC = 5 V,

TA = 25°C

SN54ABT162841 SN74ABT162841

UNIT

MIN MAX MIN MAX MIN MAX

t

w

Pulse duration, LE high or low 4 4 4 ns

t

su

Setup time, data before LE↓ 0.8 0.8 0.8 ns

t

h

Hold time, data after LE↓ 1.8 1.8 1.8 ns

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ABT162841, SN74ABT162841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

L

= 50 pF (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC = 5 V,

TA = 25°C

SN54ABT162841 SN74ABT162841

UNIT

(INPUT)

(OUTPUT)

MIN TYP MAX MIN MAX MIN MAX

t

PLH

2.1 3.5 4.5 2.1 5.7 2.1 5.2

t

PHL

D

Q

3 4.3 5.3 3 6.2 3 6

ns

t

PLH

2.1 3.5 4.5 2.1 5.6 2.1 5.4

t

PHL

LE

Q

2.8 4.1 5.1 2.8 6.1 2.8 5.8

ns

t

PZH

2 3.6 4.7 2 5.8 2 5.7

t

PZL

OE

Q

3 4.6 5.7 3 6.7 3 6.5

ns

t

PHZ

2.6 4.3 5.7 2.6 6.6 2.6 6.5

t

PLZ

OE

Q

2.2 3.6 5.8 2.2 8.4 2.2 7.1

ns

SN54ABT162841, SN74ABT162841

20-BIT BUS-INTERFACE D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS665B – JUNE 1996 – REVISED MA Y 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

1.5 V

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

7 V

Open

GND

500 Ω

500 Ω

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V 1.5 V

3 V

0 V

3 V

0 V

1.5 V

t

w

Input

VOLTAGE WA VEFORMS

SETUP AND HOLD TIMES

VOLTAGE WA VEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WA VEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

3 V

0 V

1.5 V1.5 V

Input

1.5 V

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

1.5 V1.5 V

3.5 V

0 V

1.5 V
VOL + 0.3 V

1.5 V

VOH – 0.3 V

≈ 0 V

3 V

VOLTAGE WA VEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

7 V

Open

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

Figure 1. Load Circuit and Voltage Waveforms

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