Datasheet SN74ABT162823ADGGR, SN74ABT162823ADL, SN74ABT162823ADLR Datasheet (Texas Instruments)
Page 1
SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
D
Members of the Texas Instruments
Widebus
D
Output Ports Have Equivalent 25-Ω Series
Family
Resistors So No External Resistors Are
Required
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
High-Impedance State During Power Up
and Power Down
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
These 18-bit bus-interface flip-flops feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working
registers.
The ’ABT162823A can be used as two 9-bit
flip-flops or one 18-bit flip-flop. With the
clock-enable (CLKEN
flip-flops enter data on the low-to-high transitions
of the clock. Taking CLKEN high disables the
clock buffer , thus latching the outputs. Taking the
clear (CLR
) input low causes the Q outputs to go
low independently of the clock.
) input low, the D-type
SN54ABT162823A . . . WD PACKAGE
SN74ABT162823A . . . DL PACKAGE
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
A buffered output-enable (OE) input places the nine outputs in either a normal logic state (high or low level) or
a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to
reduce overshoot and undershoot.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
description (continued)
When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT162823A is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABT162823A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
OE
CLR CLKEN
L L X X X L
L HL↑ HH
L HL↑ LL
L HLLX Q
L HHXX Q
H X X X X Z
CLK D
OUTPUT
Q
0
0
2
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Page 3
SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
logic symbol
†
2
1OE
1CLR
1CLKEN
1CLK 3C4
2CLR
2CLKEN
2CLK
1
55
56
27
2OE
28
30
29
54
1D1 1Q1
52
1D2 1Q2
51
1D3 1Q3
49
1D4
48
1D5
47
1D6
45
1D7
44
1D8
43
1D9 1Q9
42
2D1 2Q1
41
2D2
40
2D3 2Q3
38
2D4
37
2D5
36
2D6
34
2D7 2Q7
33
2D8 2Q8
31
2D9 2Q9
EN1
R2
G3
EN5
R6
G7
4D
8D
7C8
1, 2
5, 6
10
12
13
14
15
16
17
19
20
21
23
24
26
3
5
6
8
1Q4
9
1Q5
1Q6
1Q7
1Q8
2Q2
2Q4
2Q5
2Q6
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
logic diagram (positive logic)
2
1OE
1
1CLR
1CLKEN
1CLK
1D1
2OE
2CLR
2CLKEN
2CLK
2D1
55
56
54
27
28
30
29
42
CE
R
C1
1D
To Eight Other Channels
CE
R
C1
1D
To Eight Other Channels
15
3
1Q1
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except through-hole packages, which use a trace length
of zero.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
O
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 2): DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
4
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Page 5
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
V
V
V
CC
SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT162823A SN74ABT162823A
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
I
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL-voltage level rather than VCC or GND.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –12 –12 mA
Low-level output current 12 12 mA
Input transition rise or fall rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
TA = 25°C SN54ABT162823A SN74ABT162823A
MIN TYP†MAX MIN MAX MIN MAX
IK
OH
OL
§
CC
i
o
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –1 mA 3 3 3
= 4.5
CC
= 4.5
CC
VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
‡
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
‡
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –25 –55 –100 –25 –100 –25 –100 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
¶
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 9 pF
OZH
and I
include the input leakage current.
OZL
IOH = –3 mA 2.4 2.4 2.4
IOH = –12 mA 2* 2
IOL = 8 mA 0.4 0.8 0.8 0.65
IOL = 12 mA 0.8
= X
= X
Outputs high 50 50 50 µA
Outputs high 0.5 0.5 0.5
Outputs low 80 80 80 mA
Outputs disabled 0.5 0.5 0.5
±50 ±50 ±50 µA
±50 ±50 ±50 µA
1.5 1.5 1.5 mA
CC
0 V
CC
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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5
Page 6
SN54ABT162823A, SN74ABT162823A
twPulse duration
ns
t
Hold ti
CLK↑
ns
(INPUT)
(OUTPUT)
CLK
Q
ns
OE
Q
ns
OE
Q
ns
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
f
clock
t
su
h
Clock frequency 0 150 0 150 0 150 MHz
CLR low 3.3 3.3 3.3
CLK high or low 3.3 3.3 3.3
CLR inactive 1.6 2 1.6
Setup time before CLK↑
me after
Data
CLKEN low 2.8 2.8 2.8
Data 1.2 1.2 1.2
CLKEN low 0.6 0.6 0.6
2 2 2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
CLR
TO
Q 2.8 5 6.3 2.8 7.2 2.8 7 ns
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
150 150 150 MHz
2.3 4.6 6.2 2.3 8.4 2.3 7.5
2.8 4.6 6.1 2.8 7.1 2.8 6.7
1.7 3.8 5 1.7 5.8 1.7 5.9
3 5 6.1 3 7.2 3 7
2.6 4.8 6.1 2.6 7.3 2.6 6.6
1.9 4.6 6.7 1.9 10.2 1.9 9
SN54ABT162823A SN74ABT162823A
SN54ABT162823A SN74ABT162823A
UNIT
ns
UNIT
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
SN54ABT162823A, SN74ABT162823A
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS666A – JULY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
1.5 V
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
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7
Page 8
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