Datasheet SN74ABT16244ADGGR, SN74ABT16244ADGVR, SN74ABT16244ADL, SN74ABT16244ADLR Datasheet (Texas Instruments)

SN54ABT16244, SN74ABT16244A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

Typical V

(Output Ground Bounce)

OLP

< 1 V at VCC = 5 V, TA = 25°C

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The SN54ABT16244 and SN74ABT16244A are
16-bit buffers and line drivers designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. These devices can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer .
These devices provide true outputs and
symmetrical OE
inputs.

(active-low output-enable)

SN74ABT16244A . . . DGG, DGV, OR DL PACKAGE

SN54ABT16244 . . . WD PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

2OE
1A1
1A2
GND
1A3
1A4
V

CC

2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V

CC

4A1
4A2
GND
4A3
4A4
3OE

1OE

1Y1
1Y2

GND

1Y3
1Y4

V

CC

2Y1
2Y2

GND

2Y3
2Y4
3Y1
3Y2

GND

3Y3
3Y4

V

CC

4Y1
4Y2

GND

4Y3
4Y4

4OE

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16244A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OE

L H H
L LL

H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUTPUT

A

Y

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

logic symbol

†

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4

1
48
25
24

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

EN1
EN2
EN3
EN4

11
12
13
14
16
17
19
20
22
23

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4

1

1

1

2

1

3

1

4

1OE
2OE

3OE
4OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

SN54ABT16244, SN74ABT16244A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

1OE

1A1

1A2

1A3

1A4

2OE

2A1

2A2

2A3

2A4

1

47

46

44

43

48

41

40

38

37

11

12

25

3OE

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2

2Y3

2Y4

3A1

3A2

3A3

3A4

4OE

4A1

4A2

4A3

4A4

36

35

33

32

24

30

29

27

26

13

14

16

17

19

20

22

23

3Y1

3Y2

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT16244 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

SN74ABT16244A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT16244, SN74ABT16244A

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

VOLV

4.5 V

V

V

CC

,

16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

recommended operating conditions (see Note 3)

SN54ABT16244 SN74ABT16244A

MIN MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V

V
I

I

I

OZH

I

OZL

I

off

I

CEX

I

O

I

CC

∆I

C
C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

Characteristics for TA = 25°C apply to the SN74ABT16244A only.

‡

All typical values are at VCC = 5 V.

§

This data sheet limit may vary among suppliers.

¶

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

#

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

†

100 mV

SN54ABT16244 SN74ABT16244A

§

§

0.05 1.5 0.05

IK

OH

hys

¶

CC

i
o

#

Data
inputs

Control
inputs

TA = 25°C

MIN TYP‡MAX MIN MAX MIN MAX

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

= 4.5

CC

=

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

=

= 5.5 V,
IO = 0,
VI = VCC or GND

VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 8 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

Outputs high 50 50 50 µA

Outputs high 3 2 3
Outputs low 32 32 32
Outputs disabled 3 2 3

Outputs enabled 0.05 1.5 0.05

Outputs disabled 0.05 1 0.05

CC

10 10

–10 –10

0 V

CC

V

§

µA

§

µA

mA

mA

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

A

Y

ns

OE

Y

ns

OE

Y

ns

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ABT16244, SN74ABT16244A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

TO

(OUTPUT)

TO

(OUTPUT)

SN54ABT16244

VCC = 5 V,

TA = 25°C

MIN TYP MAX

0.7 2.3 3.2 0.7 3.6

0.5 2.6 3.7 0.5 4.2

0.7 3 4 0.7 4.9

0.9 3.2 5.5 0.9 6.5

1.7 3.6 5 1.7 6

1.5 2.9 4.7 1.5 5.7

SN74ABT16244A

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.3 3.2 1 3.5
1 2.6 3.7 1 4.1
1 3 3.8 1 4.8
1 3.2 4 1 4.8
1 3.6 4.4 1 4.8
1 2.9 3.7 1 4.1

MIN MAX

MIN MAX

UNIT

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54ABT16244, SN74ABT16244A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS073G – SEPTEMBER 1991 – REVISED MA Y 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated