Datasheet SN74ABT16240ADGGR, SN74ABT16240ADGVR, SN74ABT16240ADL, SN74ABT16240ADLR, SNJ54ABT16240AWD Datasheet (Texas Instruments)

SN54ABT16240A, SN74ABT16240A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

T ypical V
at V

D

Distributed VCC and GND Pin Configuration

= 5 V, TA = 25°C

CC

(Output Ground Bounce) < 1 V

OLP

Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Latch-Up Performance Exceeds 500 mA
Per JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

The ’ABT16240A devices are 16-bit buffers and
line drivers designed specifically to improve both
the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.

SN54ABT16240A . . . WD PACKAGE

SN74ABT16240A . . . DGG, DGV, OR DL PACKAGE

1OE

1Y1
1Y2

GND

1Y3
1Y4

V

CC

2Y1
2Y2

GND

2Y3
2Y4
3Y1
3Y2

GND

3Y3
3Y4

V

CC

4Y1
4Y2

GND

4Y3
4Y4

4OE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

2OE
1A1
1A2
GND
1A3
1A4
V

CC

2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V

CC

4A1
4A2
GND
4A3
4A4
3OE

These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide
inverting outputs and symmetrical active-low output-enable (OE

T o ensure the high-impedance state during power up or power down, OE

) inputs.

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16240A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT16240A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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1

SN54ABT16240A, SN74ABT16240A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OE A

L H L
L LH

HXZ

OUTPUT

Y

logic symbol

†

1

1OE
2OE
3OE

4OE

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4

48
25
24

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

EN1
EN2

EN3
EN4

11

12

13

14

11
12
13
14
16
17
19
20
22
23

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

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logic diagram (positive logic)

SN54ABT16240A, SN74ABT16240A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

1OE

1A1

1A2

1A3

1A4

2OE

2A1

2A2

2A3

2A4

1

47

46

44

43

48

41

40

38

37

11

12

25

3OE

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2

2Y3

2Y4

3A1

3A2

3A3

3A4

4OE

4A1

4A2

4A3

4A4

36

35

33

32

24

30

29

27

26

13

14

16

17

19

20

22

23

3Y1

3Y2

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, I

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

: SN54ABT16240A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

O

SN74ABT16240A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

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3

SN54ABT16240A, SN74ABT16240A

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

VOLV

4.5 V

V

V

CC

§

,

16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

recommended operating conditions (see Note 3)

SN54ABT16240A SN74ABT16240A

MIN MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

V

V
I

I

I

OZH

I

OZL

I

off

I

CEX

I

O

I

CC

∆I

C
C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

IK

OH

hys

‡

Data
inputs

CC

Control
inputs

i
o

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

= 4.5

CC

=

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA

=

= 5.5 V,
IO = 0,
VI = VCC or GND

VCC = 5.5 V,
One input at 3.4 V ,
Other inputs at
VCC or GND

VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3.5 pF
VO = 2.5 V or 0.5 V 7.5 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

Outputs high 50 50 50 µA

Outputs high 3 3 3
Outputs low 34 34 34
Outputs disabled 3 3 3

Outputs enabled 1 1.5 1

Outputs disabled 0.05 1 0.05

, literature number SCBA004.

TA = 25°C SN54ABT16240A SN74ABT16240A

MIN TYP†MAX MIN MAX MIN MAX

100 mV

1.5 1.5 1.5

CC

0 V

CC

V

mA

mA

4

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A

Y

ns

OE

Y

ns

OE

Y

ns

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ABT16240A, SN74ABT16240A

16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

TO

(OUTPUT)

TO

(OUTPUT)

SN54ABT16240A

VCC = 5 V,

TA = 25°C

MIN TYP MAX

0.8 2.7 3.8 0.8 4.8

1.1 3.1 4.3 1.1 4.9

1.3 3.3 4.3 1.3 5.4

1.4 3.4 6.2 1.4 7.2

1.6 3.6 6.2 1.6 7.2

1.4 3 5.1 1.4 5.7

SN74ABT16240A

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.7 3.8 1 4.7

1.1 3.1 4.3 1.1 4.8

1.3 3.3 4.3 1.3 5.3

1.4 3.4 6.2 1.4 7.1

1.6 3.6 4.8 1.6 6.1

1.4 3 5.1 1.4 5.6

MIN MAX

MIN MAX

UNIT

UNIT

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5

SN54ABT16240A, SN74ABT16240A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Output

Control

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

6

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Copyright  1998, Texas Instruments Incorporated