Datasheet SN65LVDS3486BD Specification

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1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1B 1A 1Y

G 2Y 2A 2B

GND

4B 4A 4Y G 3Y 3A 3B

SN65LVDT32B

1 2 3 4

8 7 6 5

1Y 2Y

GND

1A 1B 2A 2B

D PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

SN65LVDS32B

G G

1A 1B

2A 2B

3A 3B 4A 4B

Logic Diagram

(positive logic)

SN65LVDT32B ONLY (4 Places)

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

1B 1A 1Y

1,2EN

2Y 2A 2B

GND

4B 4A 4Y 3,4EN 3Y 3A 3B

SN65LVDT3486B

D PACKAGE

(TOP VIEW)

SN65LVDS3486B

1A 1B

2A 2B

3A 3B 4A 4B

Logic Diagram

(positive logic)

SN65LVDT3486B ONLY (4 Places)

1,2EN

3,4EN

1A 1B

2A 2B

SN65LVDT9637B ONLY

SN65LVDT9637B

SN65LVDS9637B

Logic Diagram

(positive logic)

HIGH-SPEED DIFFERENTIAL RECEIVERS

FEATURES

• Meets or Exceeds the Requirements of ANSI

EIA/TIA-644 Standard for Signaling Rates to 400 Mbps

• Operates With a Single 3.3-V Supply

• –2-V to 4.4-V Common-Mode Input Voltage

Range

• Differential Input Thresholds <50 mV With

50 mV of Hysteresis Over Entire CommonMode Input Voltage Range

• Integrated 110- Ω Line Termination Resistors

Offered With the LVDT Series

• Propagation Delay Times 4 ns (typ)

• Active Fail Safe Assures a High-Level Output

With No Input

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Inputs Remain High-Impedance on Power

Down

• Recommended Maximum Parallel Rate of

200 M-Transfer/s

• Available in Small-Outline Package With

1,27-mm Terminal Pitch

• Pin-Compatible With the AM26LS32, MC3486,

or µA9637

DESCRIPTION

This family of differential line receivers offers improved performance and features that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard, providing a better overall solution for the cabled environment. This generation of products is an extension to TI's overall product portfolio and is not necessarily a replacement for older LVDS receivers.

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

(1)

(1) Signaling rate, 1/t, where t is the minimum unit interval and is

expressed in the units bit/s (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of –4 to 5 V in their SN65LVDS/T33 and SN65LVDS/T34.

Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault conditions. This feature may also be used for wired-OR bus signaling.

The intended application of these devices and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and SN65LVDT9637B are characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PART NUMBER

SN65LVDS32BD 4 No LVDS32B

SN65LVDT32BD 4 Yes LVDT32B SN65LVDS3486BD 4 No LVDS3486 SN65LVDT3486BD 4 Yes LVDT3486 SN65LVDS9637BD 2 No DK637B SN65LVDT9637BD 2 Yes DR637B

(1) Add the suffix R for taped and reeled carrier.

(1)

NUMBER OF TERMINATION

RECEIVERS RESISTOR

SYMBOLIZATION

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FUNCTION TABLES

SN65LVDS32B and SN65LVDT32B

DIFFERENTIAL INPUT ENABLES

A-B G G Y

VID≥ –32 mV

–100 mV < VID≤ –32 mV

VID≤ –100 mV

X L H Z

Open

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

SN65LVDS3486B and SN65LVDT3486B

DIFFERENTIAL INPUT ENABLES

A-B EN Y

VID≥ –32 mV H H

–100 mV < VID≤ –32 mV H ?

VID≤ –100 mV H L

X L Z

Open H H

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

(1)

H X H X L H

H X ? X L ?

H X L X L L

H X H X L H

(1)

OUTPUT

(1)

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

SN65LVDS9637B and SN65LVDT9637B

DIFFERENTIAL INPUT OUTPUT

A-B Y

VID≥ -32 mV H

–100 mV < VID≤ -32 mV ?

VID≤ -100 mV L

Open H

(1) H = high level, L = low level, ? = indeterminate

(1)

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37 Ω

7 V

Y Output

LVDT Only 110 Ω

7 V

300 kΩ

50 Ω

Enable

Inputs

300 kΩ

(G Only)

(EN and G Only)

7 V

Attenuation

Network

A Input

Attenuation

Network

B Input

7 V

Attenuation

Network

60 kΩ

250 kΩ

200 kΩ

1 pF

3 pF

7 V

6.5 kΩ 6.5 kΩ

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

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SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range

Voltage range A or B –4 V to 6 V

Electrostatic discharge: A, B, and GND Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with MIL-STD-883C Method 3015.7.

(2)

Enables or Y –0.5 V to V

|VA– VB| (LVDT) 1 V

(3)

DISSIPATION RATING TABLE

PACKAGE

D8 725 mW 5.8 mW/°C 377 mW

D16 950 mW 7.6 mW/°C 494 mW

TA≤ 25°C OPERATING FACTOR

POWER RATING ABOVE TA= 25°C POWER RATING

(1)

UNIT

–0.5 V to 4 V

Class 3, A: 15 kV, B: 600 V

(1)

TA= 85°C

+ 3 V

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air

flow.

RECOMMENDED OPERATING CONDITIONS

| VID| Magnitude of differential input voltage

VIor V T

Supply voltage 3 3.3 3.6 V High-level input voltage Enables 2 V Low-level input voltage Enables 0.8 V

Voltage at any bus terminal (separately or common-mode) –2 4.4 V

Operating free-air temperature –40 85 °C

MIN NOM MAX UNIT

LVDS 0.1 3 V LVDT 0.8 V

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SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

V V V V V V

I(OFF)

(1) All typical values are at 25°C and with a 3.3 V supply.

Positive-going differential input voltage threshold 50

IT1

Negative-going differential input voltage threshold –50

IT2

Differential input fail-safe voltage threshold See Table 1 and Figure 5 –32 –100 mV

IT3

Differential input voltage hysteresis, V

ID(HYS)

High-level output voltage IOH= –4 mA 2.4 V

Low-level output voltage IOL= 4 mA 0.4 V

Supply current G or EN at GND 1.1 5 mA

– V

IT1

IT2

'32B or '3486B

'9637B No load, Steady-state 8 12

SN65LVDS µA

Input current (A or B inputs)

SN65LVDT µA

Differential input current (IIA- IIB)

SN65LVDS ±3 µA SN65LVDT VID= 0.2 V, VIC= –2 V or 4.4 V 1.55 2.22 mA

SN65LVDS Power-off input current (A or B inputs)

SN65LVDT

High-level input current (enables) VIH= 2 V 10 µA Low-level input current (enables) VIL= 0.8 V 10 µA High-impedance output current ±10 µA Input capacitance, A or B input to GND VI= 0.4 sin (4E6 π t) + 0.5 V 5 pF

(1)

VIB= -2 V or 4.4 V, See Figure 1 and Figure 2

50 mV

G or EN at VCC, No load, Steady-state 16 23

VI= 0 V, Other input open ±20 VI= 2.4 V, Other input open ±20 VI= –2 V, Other input open ±40 VI= 4.4 V, Other input open ±40 VI= 0 V, Other input open ±40 VI= 2.4 V, Other input open ±40 VI= –2 V, Other input open ±80 VI= 4.4 V, Other input open ±80 VID= 100 mV, VIC= –2 V or 4.4 V,

See Figure 1

VAor VB= 0 V or 2.4 V, V VAor VB= –2 V or 4.4 V, V VAor VB= 0 V or 2.4 V, V VAor VB= –2 V or 4.4 V, V

= 0 V ±20

= 0 V ±35

= 0 V ±30

= 0 V ±50

MAX UNIT

µA

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SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

Propagation delay time, low-to-high-level output 2.5 4 6 ns

PLH

Propagation delay time, high-to-low-level output 2.5 4 6 ns

PHL

Delay time, fail-safe deactivate time 9 ns

Delay time, fail-safe activate time 0.3 1.5 µs

Pulse skew (|t

sk(p)

Output skew

sk(o)

Part-to-part skew

sk(pp)

Output signal rise time 0.8 ns

Output signal fall time 0.8 ns

Propagation delay time, high-level-to-high-impedance output 5.5 9 ns

PHZ

Propagation delay time, low-level-to-high-impedance output 4.4 9 ns

PLZ

Propagation delay time, high-impedance -to-high-level output 3.8 9 ns

PZH

Propagation delay time, high-impedance-to-low-level output 7 9 ns

PZL

- t

PHL1

(2)

|) 200 ps

PLH1

(3)

(1) All typical values are at 25°C and with a 3.3-V supply. (2) t

(3) t

is the magnitude of the time difference between the t

sk(o)

together.

is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

sk(pp)

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

or t

PLH

See Figure 3

See Figure 3 and

Figure 6

CL= 10 pF, See Figure 3 1 ns

See Figure 4

of all receivers of a single device with all of their inputs driven

PHL

(1)

MAX UNIT

150 ps

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(VIA + VIB)/2

10 pF, 2 Places

10 pF

100 Ω

†

1000 Ω

100 Ω

IT1

0 V –100 mV

100 mV

0 V V

IT2

†

Removed for testing the LVDT device

NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.

+ –

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

PARAMETER MEASUREMENT INFORMATION

Figure 1. Voltage and Current Definitions

Figure 2. V

and V

IT1

Input Voltage Threshold Test Circuit and Definitions

IT2

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CL = 10 pF

PHL

PLH

80%

20%

80%

20%

1.4 V

1 V

0.4 V

0 V

–0.4 V

1.4 V V

PARAMETER MEASUREMENT INFORMATION (continued)

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

A. All input pulses are supplied by a generator having the following characteristics: tror tf≤ 1 ns, pulse repetition rate

(PRR) = 50 Mpps, Pulsewidth = 10 ±0.2 ns . CLincludes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.

Figure 3. Timing Test Circuit and Waveforms

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G G

500 Ω

TEST

10 pF

1.2 V

PZL

PLZ

PZL

PLZ

PZH

PHZ

PZH

PHZ

2.5 V 1 V

2 V

1.4 V

0.8 V 2 V

1.4 V

0.8 V

2.5 V

1.4 V VOL +0.5 V V

1.4 V 2 V

1.4 V

0.8 V 2 V

1.4 V

0.8 V

VOH –0.5 V

1.4 V 0

TEST

G, 1,2EN,or 3,4EN

TEST

Inputs

G, 1,2EN,or 3,4EN

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse

repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.

1,2,EN, or 3,4, EN

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 4. Enable/Disable Time Test Circuit and Waveforms

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–100 mV @ 250 KHz

–32 mV @ 250 KHz

Failsafe Asserted

a) No Failsafe

b) Failsafe Asserted

1.4 V

1 V

0.4 V

0 V

–0.4 V

1.4 V V

–0.2 V

>1.5 µs

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

Table 1. Receiver Minimum and Maximum V

APPLIED VOLTAGES

VIA(mV) VIB(mV) VID(mV) VIC(mV) Output

–2000 –1900 –100 –1950 L –2000 –1968 –32 –1984 H

4300 4400 –100 4350 L 4368 4400 –32 4384 H

(1) These voltages are applied for a minimum of 1.5 µs.

(1)

Input Threshold Test Voltages

IT3

RESULTANT INPUTS

Figure 5. V

Failsafe Threshold Test

IT3

Figure 6. Waveforms for Failsafe Activate and Deactivate

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IOL − Low-Level Output Current − mA

20 30

= 3.3 V

TA = 25°C

− Low-Level Output Voltage − V

IOH − High-Level Output Current − mA

− High-Level Output Voltage − V

−30 −20−40 0−10

= 3.3 V

TA = 25°C

4.5

3.5

−50 0 50

100

TA − Free-Air Temperature − °C

VCC = 3 V

VCC = 3.6 V

VCC = 3.3 V

− Low-To-High Propagation Delay T ime − ns

PLH

4.5

3.5

−50 0 50

100

TA − Free-Air Temperature − °C

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

− High-To-Low Propagation Delay T ime − ns

PHL

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT

LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIME

FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE

vs vs

Figure 7. Figure 8.

vs vs

Figure 9. Figure 10.

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0 100

100

120

150 200

− Supply Current − mAI CC

f − Switching Frequency − MHz

VCC = 3 V

VCC = 3.6 V

VCC = 3.3 V

140

TYPICAL CHARACTERISTICS (continued)

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

SUPPLY CURRENT

FREQUENCY

Figure 11.

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GND

13 12 11

100 Ω

100 Ω (see Note B)

100 Ω

See Note C

≈3.6 V

0.1 µF (see Note A)

1N645

(2 places)

0.01 µF

5 V

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

APPLICATION INFORMATION

A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V

plane. The capacitor should be located as close as possible to the device terminals.

B. The termination resistance value should match the nominal characteristic impedance of the transmission media with

±10%.

C. Unused enable inputs should be tied to V

or GND as appropriate.

and the ground

Figure 12. Operation with 5-V Supply

RELATED INFORMATION

IBIS modeling is available for this device. contact the local TI sales office or the TI Web site at www.ti.com for more information.

For more application guidelines, see the following documents:

• Low-Voltage Differential Signaling Design Notes (SLLA014 )

• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038 )

• Reducing EMI With LVDS (SLLA030 )

• Slew Rate Control of LVDS Circuits (SLLA034 )

• Using an LVDS Receiver With RS-422 Data (SLLA031 )

• Evaluating the LVDS EVM (SLLA033 )

TERMINATED FAILSAFE

A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves the limitations seen in present solutions. A detailed theory of operation is presented in application note The Active Fail-Safe Feature of the SN65LVDS32A (SLLA082 ).

Figure 13 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to a

high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a window comparator. The window comparator has a much slower response than the main receiver and detects when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs. When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.

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Main Receiver

A > B + 80 mV

B > A + 80 mV

Failsafe

Timer

Failsafe

Output Buffer

Reset

Window Comparator

A B

R3 R3

5 Meters of CAT-5

R1 R1

R3 = 240 Ω

R1 = 50 Ω R2 = 50 Ω

LVDSLV/PECL

APPLICATION INFORMATION (continued)

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

Figure 13. Receiver With Terminated Failsafe

ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER

The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of choice for system designers. Designers know of the established technology and that it is capable of high-speed data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the termination bias voltage required for ECL termination (V

Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received

by TI's wide common-mode receiver and the resulting eye pattern. The values for R3 are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the characteristic load impedance of 50 Ω . The R2 resistor is a small value and is intended to minimize any possible common-mode current reflections.

– 2 V).

Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver

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Tektronix PS25216

Programmable

Power Supply

Bench Test Board

Tektronix HFS 9003

Stimulus System

Tektronix TDS 784D 4-Channel Digital Phosphor Oscilloscope

– DPO

Trigger

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

APPLICATION INFORMATION (continued)

Figure 15. LV/PECL to Remote SN65LVDS32B at 500 Mbps Receiver Output (CH1)

TEST CONDITIONS

• V

• TA= 25°C (ambient temperature)

• All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ

= 3.3 V

data.

EQUIPMENT

• Tektronix PS25216 programmable power supply

• Tektronix HFS 9003 stimulus system

• Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO

Figure 16. Equipment Setup

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100 Mbit/s 200 Mbit/s

APPLICATION INFORMATION (continued)

SN65LVDS32B , , SN65LVDT32B SN65LVDS3486B , SN65LVDT3486B SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

Figure 17. Typical Eye Pattern SN65LVDS32B

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

SN65LVDS32BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32B

SN65LVDS32BDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32B

SN65LVDS32BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS32B

SN65LVDS3486BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486B

SN65LVDS3486BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS3486B

SN65LVDS9637BD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DK637B

SN65LVDS9637BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DK637B

SN65LVDT32BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT32B

SN65LVDT32BDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT32B

SN65LVDT32BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT32B

SN65LVDT3486BD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT3486B

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

10-Dec-2020

Samples

(4/5)

SN65LVDT3486BDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDT3486B

SN65LVDT9637BD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DR637B

SN65LVDT9637BDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DR637B

SN65LVDT9637BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DR637B

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

Page 19

PACKAGE OPTION ADDENDUM

www.ti.com

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

10-Dec-2020

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

Page 20

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

SN65LVDS32BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS3486BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

SN65LVDT32BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDT3486BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDT9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 21

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65LVDS32BDR SOIC D 16 2500 340.5 336.1 32.0 SN65LVDS3486BDR SOIC D 16 2500 350.0 350.0 43.0 SN65LVDS9637BDR SOIC D 8 2500 340.5 336.1 25.0

SN65LVDT32BDR SOIC D 16 2500 350.0 350.0 43.0 SN65LVDT3486BDR SOIC D 16 2500 350.0 350.0 43.0 SN65LVDT9637BDR SOIC D 8 2500 340.5 336.1 25.0

Pack Materials-Page 2

Page 22

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SN65LVDS32BD D SOIC 16 40 507 8 3940 4.32

SN65LVDS32BDG4 D SOIC 16 40 507 8 3940 4.32

SN65LVDS3486BD D SOIC 16 40 505.46 6.76 3810 4 SN65LVDS9637BD D SOIC 8 75 507 8 3940 4.32 SN65LVDS9637BD D SOIC 8 75 505.46 6.76 3810 4

SN65LVDT32BD D SOIC 16 40 505.46 6.76 3810 4

SN65LVDT32BDG4 D SOIC 16 40 505.46 6.76 3810 4

SN65LVDT3486BD D SOIC 16 40 505.46 6.76 3810 4 SN65LVDT9637BD D SOIC 8 75 507 8 3940 4.32

SN65LVDT9637BD D SOIC 8 75 505.46 6.76 3810 4 SN65LVDT9637BDG4 D SOIC 8 75 507 8 3940 4.32 SN65LVDT9637BDG4 D SOIC 8 75 505.46 6.76 3810 4

Pack Materials-Page 3

Page 23

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