Datasheet SN54LS373J Specification

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

D

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package

D

3-State Bus-Driving Outputs

D

Full Parallel Access for Loading

D

Buffered Control Inputs

D

Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)

D

P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

SN54LS373, SN54LS374, SN54S373,

SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE

SN54S374 . . . J OR W PACKAGE

SN74LS374 . . . DB, DW, N, OR NS PACKAGE

SN74S373 . . . DW OR N PACKAGE

†

C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

SN54LS373, SN54LS374, SN54S373,

SN54S374 . . . FK PACKAGE

2D 2Q 3Q 3D 4D

†

C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

(TOP VIEW)

1

OC

2

1Q

3

1D

4

2D

5

2Q

6

3Q

7

3D

8

4D

9

4Q

GND

10

(TOP VIEW)

1D1QOC

3212019

4 5 6 7 8

910111213

4Q

†

GND

20

V

CC

19

8Q

18

8D

17

7D

16

7Q

15

6Q

14

6D

13

5D

12

5Q

†

11

C

CC

8Q

V

8D

18

7D

17

7Q

16

6Q

15

6D

14

5D

C

5Q

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC

) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC

does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new

data can be entered, even while the outputs are off.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SN54LS373, SN54LS374, SN54S373, SN54S374,

PDIP

N

LS373

LS374

0°C to 70°C

SOIC

DW

S373

S374

CDIP

J

LCCC

FK

SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

ORDERING INFORMATION

T

A

°

SOP – NS

SSOP – DB Tape and reel SN74LS374DBR LS374A

–55°C to 125°C

CFP – W

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

PACKAGE

–

†

Tube SN74LS373N SN74LS373N Tube SN74LS374N SN74LS374N Tube SN74S373N SN74S373N Tube SN74S374N SN74S374N Tube SN74LS373DW Tape and reel SN74LS373DWR Tube SN74LS374DW Tape and reel SN74LS374DWR Tube SN74S373DW Tape and reel SN74S373DWR Tube SN74S374DW Tape and reel SN74S374DWR Tape and reel SN74LS373NSR 74LS373 Tape and reel SN74LS374NSR 74LS374 Tape and reel SN74S374NSR 74S374

Tube SN54LS373J SN54LS373J Tube SNJ54LS373J SNJ54LS373J Tube SN54LS374J SN54LS374J Tube SNJ54LS374J SNJ54LS374J Tube SN54S373J SN54S373J Tube SNJ54S373J SNJ54S373J Tube SN54S374J SN54S374J Tube SNJ54S374J SNJ54S374J Tube SNJ54LS373W SNJ54LS373W Tube SNJ54LS374W SNJ54LS374W Tube SNJ54S374W SNJ54S374W Tube SNJ54LS373FK SNJ54LS373FK Tube SNJ54LS374FK SNJ54LS374FK Tube SNJ54S373FK SNJ54S373FK Tube SNJ54S374FK SNJ54S374FK

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

Function Tables

’LS373, ’S373

(each latch)

INPUTS

OC C D

L H H H L HL L

L LX Q

H X X Z

’LS374, ’S374

(each latch)

INPUTS

OC CLK D

L ↑ H H L ↑ LL

L LX Q

H X X Z

OUTPUT

Q

0

OUTPUT

Q

0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

logic diagrams (positive logic)

OC

1D

2D

3D

4D

5D

’LS373, ’S373

Transparent Latches

1

11

C

3

4

7

8

13

C1 1D

12

2

1Q

5

2Q

6

3Q

9

4Q

5Q

OC

CLK

1D

2D

3D

4D

5D

Positive-Edge-Triggered Flip-Flops

1

11

3

4

7

8

13

’LS374, ’S374

C1

1D

C1

1D

C1

1D

C1

1D

C1

1D

12

2

1Q

5

2Q

6

3Q

9

4Q

5Q

14

6D

17

7D

18

8D

Pin numbers shown are for DB, DW, J, N, NS, and W packages.

C1 1D

for ’S373 Only

15

16

19

6Q

7Q

8Q

6D

7D

8D

14

17

18

C1

1D

C1

1D

C1

1D

for ’S374 Only

15

16

19

6Q

7Q

8Q

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

schematic of inputs and outputs

’LS373

EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- AND

V

CC

Req = 20 kΩ NOM

Input

OUTPUT-CONTROL INPUTS

V

CC

Input

17 kΩ NOM

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

TYPICAL OF ALL OUTPUTS

V

CC

100 Ω NOM

Output

EQUIVALENT OF DATA INPUTS

V

CC

30 kΩ NOM

Input

’LS374

EQUIVALENT OF CLOCK- AND

OUTPUT-CONTROL INPUTS

V

CC

17 kΩ NOM

Input

TYPICAL OF ALL OUTPUTS

100 Ω NOM

V

CC

Output

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LS373, SN54LS374, SN54S373, SN54S374,

UNIT

twPulse duration

ns

tsuData setup time

ns

thData hold time

ns

SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (’LS devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. V oltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN54LS’ SN74LS’

MIN NOM MAX MIN NOM MAX

V V I

OH

I

OL

T

‡

The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).

Supply voltage 4.5 5 5 4.75 5 5.25 V

CC

High-level output voltage 5.5 5.5 V

OH

High-level output current –1 –2.6 mA Low-level output current 12 24 mA

CLK high 15 15 CLK low 15 15

p

Operating free-air temperature –55 125 0 70 °C

A

’LS373 5↓ 5↓ ’LS374 20↑ 20↑ ’LS373 20↓ 20↓

‡

’LS374

5↑ 0↑

†

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

†

UNIT

VOHHigh-level output voltage

CC

,

IH

,

2.4

3.4

2.4

3.1

V

VOLLow-level output voltage

CC

,

IH

,

V

I

,

CC

,

IH

,

20

20mA

I

,

CC

,

IH

,

20–20mA

I

V

MAX

V

7 V

0.1

mA

ICCSupply current

CC

,

mA

PARAMETER

TEST CONDITIONS

UNIT

Data

Any Q

L

,

L

,

ns

C or CLK

Any Q

L

,

L

,

ns

OC

Any Q

L

,

L

,

ns

t

152515

28

OC

Any Q

R

667 Ω

C

5 pF

ns

t

122012

20

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54LS’ SN74LS’

MIN TYP‡MAX MIN TYP‡MAX

V

High-level input voltage 2 2 V

IH

V

Low-level input voltage 0.7 0.8 V

IL

V

Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V

IK

V

p

Off-state output current, V

OZH

high-level voltage applied Off-state output current, V

OZL

low-level voltage applied Input current at maximum

I

input voltage

I

High-level input current VCC = MAX, VI = 2.7 V 20 20

IH

I

Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA

IL

I

Short-circuit output current§VCC = MAX –30 –130 –30 –130 mA

OS

pp

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

= MIN, V

VIL = VIL max, V

= MIN, V

VIL = VIL max

= MAX, V

VO = 2.7 V

= MAX, V

VO = 0.4 V

,

=

CC

V

= MAX,

Output control at 4.5 V

= 2 V,

IOH = MAX

= 2 V,

=

I

IOL = 12 mA 0.25 0.4 0.25 0.4 IOL = 24 mA 0.35 0.5

–

’LS373 24 40 24 40 ’LS374 27 40 27 40

m

A

switching characteristics, V

FROM TO

(INPUT) (OUTPUT)

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL PHZ PLZ

NOTE 3: Maximum clock frequency is tested with all outputs loaded. f

= maximum clock frequency

max

t

= propagation delay time, low-to-high-level output

PLH

t

= propagation delay time, high-to-low-level output

PHL

t

= output enable time to high level

PZH

t

= output enable time to low level

PZL

t

= output disable time from high level

PHZ

t

= output disable time from low level

PLZ

= 5 V, TA = 25°C (see Figure 1)

CC

RL = 667 Ω, CL = 45 pF,

See Note 3

R

= 667 Ω, C

See Note 3

R

= 667 Ω, C

See Note 3

R

= 667 Ω, C

See Note 3

,

=

L

= 45 pF,

p

=

L

’LS373 ’LS374

MIN TYP MAX MIN TYP MAX

35 50 MHz

12 18 12 18 20 30 15 28 18 30 19 28 15 28 20 26 25 36 21 28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

schematic of inputs and outputs

’S373 and ’S374 ’S373 and ’S374

EQUIVALENT OF EACH INPUT

V

CC

2.8 kΩ NOM

Input

TYPICAL OF ALL OUTPUTS

50 Ω NOM

V

CC

Output

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

twPulse duration, clock/enable

ns

tsuData setup time

ns

thData hold time

ns

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (’S devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

V V I

T

OH

Supply voltage 4.5 5 5.5 4.75 5 5.25 V

CC

High-level output voltage 5.5 5.5 V

OH

High-level output current –2 –6.5 mA

Operating free-air temperature –55 125 0 70 °C

A

5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

SN54S’ SN74S’

MIN NOM MAX MIN NOM MAX

High 6 6 Low 7.3 7.3

p

’S373 0↓ 0↓ ’S374 5↑ 5↑ ’S373 10↓ 10↓ ’S374 2↑ 2↑

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

SN54LS373, SN54LS374, SN54S373, SN54S374,

V

MIN

V

2 V

V

0.8 V

I

MAX

V

’S374

PARAMETER

TEST CONDITIONS

UNIT

Data

Any Q

L

,

L

,

ns

C or CLK

Any Q

L

,

L

,

ns

OC

Any Q

L

,

L

,

ns

OC

Any Q

R

280 Ω,C

5 pF

ns

SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)

=

†

,

OH

=

MIN

2.4 3.4

2.4 3.1

PARAMETER

V

IH

V

IL

V

IK

SN54S’

OH

SN74S’

V

OL

I

OZH

I

OZL

I

IH

I

IL

§

I

OS

I

CC

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

All typical values are at VCC= 5 V, TA = 25°C.

§

Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

VCC = MIN, II = –18 mA –1.2 V

,

=

CC

VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V VCC = MAX, VIH = 2 V, VO = 2.4 V 50 VCC = MAX, VIH = 2 V, VO = 0.5 V –50 VCC = MAX, VI = 5.5 V 1 mA VCC = MAX, VI = 2.7 V 50 VCC = MAX, VI = 0.5 V –250 VCC = MAX –40 –100 mA

VCC = MAX

IH

’S373

’

TEST CONDITIONS

,

=

IL

Outputs high 160 Outputs low 160 Outputs disabled 190 Outputs high 110 Outputs low 140 Outputs disabled 160 CLK and OC at 4 V, D inputs at 0 V 180

‡

TYP

2 V

MAX UNIT

0.8 V

mA

m

A

m

A

m

A

m

A

switching characteristics, V

FROM TO

(INPUT) (OUTPUT)

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

NOTE 3. Maximum clock frequency is tested with all outputs loaded. f

= maximum clock frequency

max

t

= propagation delay time, low-to-high-level output

PLH

t

= propagation delay time, high-to-low-level output

PHL

t

= output enable time to high level

PZH

t

= output enable time to low level

PZL

t

= output disable time from high level

PHZ

t

= output disable time from low level

PLZ

= 5 V, TA = 25°C (see Figure 2)

CC

RL = 280 Ω, CL = 15 pF,

See Note 3

R

= 280 Ω,C

See Note 3

R

= 280 Ω,C

See Note 3

R

= 280 Ω,C

See Note 3

=

L

= 15 pF,

p

=

L

’S373 ’S374

MIN TYP MAX MIN TYP MAX

75 100 MHz

7 12 7 12 7 14 8 15

12 18 11 17

8 15 8 15

11 18 11 18

6 9 5 9 8 12 7 12

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

Test

Point

C

L

V

CC

R

L

(see Note B)

From Output

Under Test

(see Note A)

CC

V

CC

R

L

Test Point

C

L

From Output

Under Test

(see Note A)

Test

R

Point

C

L

S1

(see Note B)

5 kΩ

S2

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

t

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for t E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. H. All parameters and waveforms are not applicable to all devices .

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

t

PHL

t

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

V

OH

V

OL

V

OH

V

OL

, and t

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

t

PZL

Waveform 1

(see Notes C

and D)

t

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

PLZ

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V

t

su

1.3 V 1.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.3 V 1.3 V

1.3 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

3 V

0 V

t

h

3 V

0 V

3 V

0 V

t

PLZ

≈1.5 V VOL + 0.5 V

V

OL

t

PHZ

V

OH

VOH – 0.5 V ≈1.5 V

.

PZL

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54S/74S DEVICES

V

From Output

Under Test

(see Note A)

Test

Point

C

L

V

CC

R

L

(see Note B)

From Output

Under Test

(see Note A)

CC

V

CC

R

L

Test Point

C

L

From Output

Under Test

(see Note A)

Test

R

Point

C

L

1 kΩ

S1

(see Note B)

S2

FOR 2-STATE TOTEM-POLE OUTPUTS

High-Level

Low-Level

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

LOAD CIRCUIT

Pulse

Input

t

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.

F. The outputs are measured one at a time with one input transition per measurement.

G. All parameters and waveforms are not applicable to all devices .

1.5 V 1.5 V

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

, t

PLH

PHL

t

PHL

t

PLH

, t

FOR OPEN-COLLECTOR OUTPUTS

PHZ

LOAD CIRCUIT

3 V

0 V

V

OH

V

OL

V

OH

V

OL

, and t

PLZ

Timing

Input

Data

Input

Output

Control

(low-level

enabling)

t

PZL

Waveform 1

(see Notes C

and D)

t

PZH

Waveform 2

(see Notes C

and D)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

; S1 is open and S2 is closed for t

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V

VOLTAGE WAVEFORMS

; S1 is closed and S2 is open for t

PZH

3 V

0 V

t

h

3 V

0 V

3 V

0 V

t

PLZ

≈1.5 V VOL + 0.5 V

V

OL

t

PHZ

V

OH

VOH – 0.5 V ≈1.5 V

.

PZL

12

Figure 2. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54LS373, SN54LS374, SN54S373, SN54S374,

SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

TYPICAL APPLICATION DATA

Bidirectional Bus Driver

Output

Control 1

1Q 2Q 3Q 4Q

or

5Q 6Q 7Q

C

8Q

1D

C

2D 3D 4D

or

5D 6D 7D 8D

Bidirectional Data Bus 2

Clock 2

Output Control 2

Bidirectional

Data Bus 1

Clock 1

Bus

Exchange

Clock

Clock 1

Clock 2

1D 2D 3D 4D 5D 6D 7D 8D

1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

’LS374

’S374

’LS374

’S374

H

Enable Select

Clock Circuit for Bus Exchange

Expandable 4-Word by 8-Bit General Register File

1/2 SN74LS139

or SN74S139

Y0

G

Y1

A

Y2

B

Y3

1/2 SN74LS139

or SN74S139

’LS374 or ’S374

Y0 Y1 Y2 Y3

AB G

Clock

Select

Clock

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

78011022A ACTIVE LCCC FK 20 1 Non-RoHS

7801102RA ACTIVE CDIP J 20 1 Non-RoHS

7801102SA ACTIVE CFP W 20 1 Non-RoHS

JM38510/32502B2A ACTIVE LCCC FK 20 1 Non-RoHS

JM38510/32502BRA ACTIVE CDIP J 20 1 Non-RoHS

JM38510/32502BSA ACTIVE CFP W 20 1 Non-RoHS

JM38510/32502SRA ACTIVE CDIP J 20 20 Non-RoHS

JM38510/32502SSA ACTIVE CFP W 20 1 Non-RoHS

JM38510/32503B2A ACTIVE LCCC FK 20 1 Non-RoHS

JM38510/32503BRA ACTIVE CDIP J 20 1 Non-RoHS

JM38510/32503BSA ACTIVE CFP W 20 1 Non-RoHS

M38510/32502B2A ACTIVE LCCC FK 20 1 Non-RoHS

M38510/32502BRA ACTIVE CDIP J 20 1 Non-RoHS

M38510/32502BSA ACTIVE CFP W 20 1 Non-RoHS

M38510/32502SRA ACTIVE CDIP J 20 20 Non-RoHS

M38510/32502SSA ACTIVE CFP W 20 1 Non-RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& Green

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 78011022A

SNJ54LS 374FK

SNPB N / A for Pkg Type -55 to 125 7801102RA

SNJ54LS374J

SNPB N / A for Pkg Type -55 to 125 7801102SA

SNJ54LS374W

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502B2A

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502BRA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502BSA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502SRA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502SSA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32503B2A

SNPB N / A for Pkg Type -55 to 125 JM38510/

32503BRA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32503BSA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502B2A

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502BRA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502BSA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502SRA

SNPB N / A for Pkg Type -55 to 125 JM38510/

32502SSA

21-Jul-2022

Samples

(4/5)

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

M38510/32503B2A ACTIVE LCCC FK 20 1 Non-RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 JM38510/

& Green

M38510/32503BRA ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 JM38510/

& Green

M38510/32503BSA ACTIVE CFP W 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 JM38510/

& Green

SN54LS373J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SN54LS373J

& Green

SN54LS374J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SN54LS374J

& Green

SN54S373J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SN54S373J

& Green

SN54S374J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SN54S374J

& Green

SN74LS373DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS373

SN74LS373DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS373

SN74LS373N ACTIVE PDIP N 20 20 RoHS &

NIPDAU N / A for Pkg Type 0 to 70 SN74LS373N

Non-Green

SN74LS373NE4 ACTIVE PDIP N 20 20 RoHS &

NIPDAU N / A for Pkg Type 0 to 70 SN74LS373N

Non-Green

SN74LS373NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS373 SN74LS374DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS374A

SN74LS374DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS374

SN74LS374DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS374

SN74LS374N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS374N SN74LS374NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS374N SN74LS374NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS374

SN74LS374NSRG4 ACTIVE SO NS 20 2000 TBD Call TI Call TI 0 to 70

32503B2A

32503BRA

32503BSA

21-Jul-2022

Samples

(4/5)

Samples

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

SN74S373N ACTIVE PDIP N 20 20 RoHS &

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

NIPDAU N / A for Pkg Type 0 to 70 SN74S373N

Non-Green

SN74S374N ACTIVE PDIP N 20 20 RoHS &

NIPDAU N / A for Pkg Type 0 to 70 SN74S374N

Non-Green

SNJ54LS373FK ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54LS

& Green

SNJ54LS373J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54LS373J

& Green

SNJ54LS373W ACTIVE CFP W 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54LS373W

& Green

SNJ54LS374FK ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 78011022A

& Green

SNJ54LS374J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 7801102RA

& Green

SNJ54LS374W ACTIVE CFP W 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 7801102SA

& Green

SNJ54S373FK ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54S

& Green

SNJ54S373J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54S373J

& Green

SNJ54S374FK ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54S

& Green

SNJ54S374J ACTIVE CDIP J 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54S374J

& Green

SNJ54S374W ACTIVE CFP W 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 SNJ54S374W

& Green

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

21-Jul-2022

Op Temp (°C) Device Marking

(4/5)

373FK

SNJ54LS 374FK

SNJ54LS374J

SNJ54LS374W

373FK

374FK

Samples

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LS373, SN54LS373-SP, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 :

Catalog : SN74LS373, SN54LS373, SN74LS374, SN74S373, SN74S374

•

21-Jul-2022

Military : SN54LS373, SN54LS374, SN54S373, SN54S374

•

Space : SN54LS373-SP

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

•

21-Jul-2022

Addendum-Page 5

PACKAGE MATERIALS INFORMATION

Reel Width (W1)

REEL DIMENSIONS

A0 B0 K0

W

Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0

W

A0

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1

Q1Q2 Q2

Q3 Q3Q4 Q4

User Direction of Feed

P1

Reel

Diameter

www.ti.com 4-Oct-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

SN74LS373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

SN74LS373NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74LS374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74LS374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

SN74LS374NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1

Device Package

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

www.ti.com 4-Oct-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LS373DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74LS373NSR SO NS 20 2000 367.0 367.0 45.0 SN74LS374DBR SSOP DB 20 2000 356.0 356.0 35.0

SN74LS374DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74LS374NSR SO NS 20 2000 356.0 356.0 41.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 4-Oct-2022

TUBE

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

78011022A FK LCCC 20 1 506.98 12.06 2030 NA

7801102SA W CFP 20 1 506.98 26.16 6220 NA JM38510/32502B2A FK LCCC 20 1 506.98 12.06 2030 NA JM38510/32502BSA W CFP 20 1 506.98 26.16 6220 NA JM38510/32502SSA W CFP 20 1 506.98 26.16 6220 NA JM38510/32503B2A FK LCCC 20 1 506.98 12.06 2030 NA JM38510/32503BSA W CFP 20 1 506.98 26.16 6220 NA

M38510/32502B2A FK LCCC 20 1 506.98 12.06 2030 NA M38510/32502BSA W CFP 20 1 506.98 26.16 6220 NA M38510/32502SSA W CFP 20 1 506.98 26.16 6220 NA M38510/32503B2A FK LCCC 20 1 506.98 12.06 2030 NA M38510/32503BSA W CFP 20 1 506.98 26.16 6220 NA

SN74LS373DW DW SOIC 20 25 507 12.83 5080 6.6

SN74LS373N N PDIP 20 20 506 13.97 11230 4.32

SN74LS373NE4 N PDIP 20 20 506 13.97 11230 4.32

SN74LS374DW DW SOIC 20 25 507 12.83 5080 6.6

SN74LS374N N PDIP 20 20 506 13.97 11230 4.32

SN74LS374NE4 N PDIP 20 20 506 13.97 11230 4.32

SN74S373N N PDIP 20 20 506 13.97 11230 4.32 SN74S374N N PDIP 20 20 506 13.97 11230 4.32

SNJ54LS373FK FK LCCC 20 1 506.98 12.06 2030 NA

SNJ54LS373W W CFP 20 1 506.98 26.16 6220 NA

SNJ54LS374FK FK LCCC 20 1 506.98 12.06 2030 NA

SNJ54LS374W W CFP 20 1 506.98 26.16 6220 NA

SNJ54S373FK FK LCCC 20 1 506.98 12.06 2030 NA SNJ54S374FK FK LCCC 20 1 506.98 12.06 2030 NA

SNJ54S374W W CFP 20 1 506.98 26.16 6220 NA

L - Tube length

Pack Materials-Page 3

PACKAGE OUTLINE

A

7.5

6.9

NOTE 3

10

SCALE 2.000

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

0.1 C

C

SEATING PLANE

8.2

TYP

7.4 PIN 1 INDEX AREA

18X 0.65

11

20

2X

5.85

0.38

20X

0.22

0.1 C A B

1

B

5.6

5.0

NOTE 4

0 -8

0.25

0.95

0.55

A 15

DETAIL A

TYPICAL

4214851/B 08/2019

SEE DETAIL A

(0.15) TYP

GAGE PLANE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-150.

www.ti.com

2 MAX

0.05 MIN

EXAMPLE BOARD LAYOUT

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

20X (0.45)

18X (0.65)

1

10

20X (1.85)

SYMM

(R0.05) TYP

20

SYMM

11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

EXPOSED METAL

0.07 MAX ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

METAL

15.000

SOLDER MASK DETAILS

METAL UNDER SOLDER MASK

0.07 MIN ALL AROUND

SOLDER MASK

DEFINED

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

SOLDER MASK OPENING

EXPOSED METAL

4214851/B 08/2019

EXAMPLE STENCIL DESIGN

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

20X (0.45)

18X (0.65)

1

10

20X (1.85)

SYMM

(R0.05) TYP

20

SYMM

11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4214851/B 08/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

A

13.0

12.6

NOTE 3

SCALE 1.200

10.63

TYP

9.97

PIN 1 ID AREA

1

20

18X 1.27

2X

11.43

SOIC - 2.65 mm max heightDW0020A

SOIC

C

SEATING PLANE

0.1 C

10

B

7.6

7.4

NOTE 4

SEE DETAIL A

11

0.51

20X

0.31

0.25 C A B

0.33 TYP

0.10

GAGE PLANE

0 - 8

2.65 MAX

0.25

1.27

0.40

DETAIL A

TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.

5. Reference JEDEC registration MS-013.

0.3

0.1

www.ti.com

EXAMPLE BOARD LAYOUT

SOIC - 2.65 mm max heightDW0020A

SOIC

20X (2)

20X (0.6)

18X (1.27)

(R )

0.05

TYP

10

SYMM

1

20

SYMM

11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK OPENING

METAL

0.07 MAX ALL AROUND

NON SOLDER MASK

DEFINED

METAL UNDER SOLDER MASK

0.07 MIN ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SOLDER MASK OPENING

4220724/A 05/2016

www.ti.com

EXAMPLE STENCIL DESIGN

SOIC - 2.65 mm max heightDW0020A

SOIC

20X (2)

20X (0.6)

18X (1.27)

10

SYMM

1

20

SYMM

11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4220724/A 05/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet SN54LS373J Specification

Specifications and Main Features

Frequently Asked Questions

User Manual