Datasheet SN54LS323J, SN74LS323DW Datasheet (Motorola)

5-1

FAST AND LS TTL DATA

8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS

The SN54/74LS323 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Its function is similar to the SN54/74LS299 with the exception
of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate inputs and outputs are provided
for flip-flops Q0 and Q7 to allow easy cascading.

Four operation modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH transition of the
Clock.

• Common I/O for Reduced Pin Count

• Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store

• Separate Continuous Inputs and Outputs from Q

0

and Q7 Allow Easy

Cascading

• Fully Synchronous Reset

• 3-State Outputs for Bus Oriented Applications

• Input Clamp Diodes Limit High-Speed Termination Effects

• ESD > 3500 Volts

CONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

18 17 16 15 14 13

1 2 3 4 5 6

7

20 19

8

V

CC

S

0

S1DS7Q7I/O

7

I/O

3

I/O

5

I/O

1

OE

1OE2

I/O6I/O4I/O2I/O0Q

0

9 10

SR GND

12 11

CP DS

0

PIN NAMES LOADING (Note a)

HIGH LOW

CP Clock Pulse (active positive going edge) Input 0.5 U.L. 0.25 U.L.
DS

0

Serial Data Input for Right Shift 0.5 U.L. 0.25 U.L.

DS

7

Serial Data Input for Left Shift 0.5 U.L. 0.25 U.L.

I/O

n

Parallel Data Input or
Parallel Output (3-State) (Note c)

1.0 U.L.

65 (25) U.L.

0.5 U.L.

15 (7.5) U.L.

OE

1

, OE

2

3-State Output Enable (active LOW) Inputs 0.5 U.L. 0.25 U.L.

Q0, Q

7

S0, S

1

Serial Outputs (Note b)
Mode Select Inputs

10 U.L.

1 U.L.

5 (2.5) U.L.

SR Synchronous Reset (active LOW) Input 0.5 U.L. 0.25 U.L.

NOTES:
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.

The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.

SN54/74LS323

8-BIT SHIFT/STORAGE REGISTER

WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC

20

1

J SUFFIX

CERAMIC

CASE 732-03

20

1

N SUFFIX

PLASTIC

CASE 738-03

20

1

DW SUFFIX

SOIC

CASE 751D-03

5-2

FAST AND LS TTL DATA

SN54/74LS323

LOGIC DIAGRAM

S1S

0

DS

0

SR

Q

0

OE

1

OE

2

D

Q

CP

I/O

0

I/O

1

I/O

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

DS

7

Q

7

14

1

2

67

3

8

45

9

11

12

13 15 16

17

18

19

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

CP

FUNCTIONAL DESCRIPTION

The logic diagram and truth table indicate the functional

characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:

1. They use eight D-type edge-triggered flip-flops that re­spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control (S0, S1) and data inputs (DS0, DS7, I/O0–I/O7) may
be stable at least a setup time prior to the positive transition
of the Clock Pulse.

2. When S0 = S1 = 1, I/O0–I/O7 are parallel inputs to flip-flops
Q0–Q7 respectively, and the outputs of Q0–Q7 are in the
high impedance state regardless of the state of OE

1

or

OE

2

.

An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.

TRUTH TABLE

INPUTS RESPONSE

SR S1S0OE1OE2CP DS0DS

7

L X X H X X X
L X X X H X X

Synchronous Reset; Q0 = Q7 = LOW

L H H X X X X

I/O voltage undetermined

L L X L L X X Synchronous Reset; Q0 = Q7 = LOW
L X L L L X X I/O voltage LOW

H L H X X D X Shift Right; Dº Q0; Q0º Q1; etc.
H L H L L D X Shift Right; Dº Q0 & I/O0; Q0º Q1 & I/O1; etc.

H H L X X X D Shift Left; Dº Q7; Q7º Q6; etc.
H H L L L X D Shift Left; Dº Q7 & I/O7; Q7º Q6 & I/O6; etc.

H H H X X X X Parallel Load I/Onº Q

n

H L L H X X X X
H L L X H X X X

Hold; I/O Voltage Undetermined

H L L L L X X X Hold; I/On = Q

n

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

5-3

FAST AND LS TTL DATA

SN54/74LS323

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

T

A

Operating Ambient Temperature Range 54

74

–55

0

25
25

125

70

°C

I

OH

Output Current — High Q0, Q

7

54, 74 –0.4 mA

I

OL

Output Current — Low Q0, Q

7

Q0, Q

7

54
74

4.0

8.0

mA

I

OH

Output Current — High I/O0–I/O

7

I/O0–I/O

7

54
74

–1.0
–2.6

mA

I

OL

Output Current — Low I/O0–I/O

7

I/O0–I/O

7

54
74

12
24

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

54 0.7

VILInput LOW Voltage

74 0.8

V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

54 2.4 3.2 V

V

OH

Output HIGH Voltage
I/O0–I/O

7

74 2.4 3.1 V

VCC = MIN, IOH = MAX

54 2.5 3.4 V

V

OH

Output HIGH Voltage
Q0, Q

7

74 2.7 3.4 V

VCC = MIN, IOH = MAX

54, 74 0.25 0.4 V IOL = 12 mA

V

OL

Output LOW Voltage
I/O0–I/O

7

74 0.35 0.5 V IOL = 24 mA

VIN = VIL or V

IH

per Truth Table

54, 74 0.4 V IOL = 4.0 mA

V

OL

Output LOW Voltage
Q0–Q

7

74 0.5 V IOL = 8.0 mA

VIN = VIL or V

IH

per Truth Table

I

OZH

Output Off Current HIGH
I/O0–I/O

7

40 µA VCC = MAX, V

OUT

= 2.7 V

I

OZL

Output Off Current LOW
I/O0–I/O

7

–400 µA VCC = MAX, V

OUT

= 0.4 V

Others 20 µA
S0, S1,

I/O0–I/O

7

40 µA

IIHInput HIGH Current

Others 0.1 mA
S0, S

1

0.2 mA

VCC = MAX, VIN = 7.0 V

I/O0–I/O

7

0.1 mA VCC = MAX, VIN = 5.5 V

Others

–0.4 mA

I

IL

S0, S

1

–0.8 mA

VCC = MAX, VIN = 0.4 V

Qo, Q

7

–20 –100 mA VCC = MAX

OS

Short Circuit Current

(Note 1)

I/O0–I/O

7

–30 –130 mA VCC = MAX

I

CC

Power Supply Current 53 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

I

OS

Output HIGH Voltage

Output HIGH Voltage

Output LOW Voltage

Output LOW Voltage

Input LOW Current

Short Circuit Current

Guaranteed Input LOW Voltage for

VCC = MAX, VIN = 2.7 V

VCC = VCC MIN,

VCC = VCC MIN,

5-4

FAST AND LS TTL DATA

SN54/74LS323

AC CHARACTERISTICS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

f

MAX

Maximum Clock Frequency 25 35 MHz

t

PHL

t

PLH

Propagation Delay, Clock
to Q0 or Q

7

26
22

39
33

ns

t

PHL

t

PLH

Propagation Delay, Clock
to I/O0–I/O

7

25
17

39
25

ns

L

= 45 pF,

t

PZH

t

PZL

Output Enable Time

14
20

21
30

ns

CL = 45 pF,
RL = 667 Ω

t

PHZ

t

PLZ

Output Disable Time

10
10

15
15

ns CL = 5.0 pF

AC SETUP REQUIREMENTS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

t

W

Clock Pulse Width HIGH 25 ns

t

W

Clock Pulse Width LOW 15 ns

t

W

Clear Pulse Width LOW 20 ns

t

s

Data Setup Time 20 ns

t

s

Select Setup Time 35 ns

VCC = 5.0 V

t

h

Data Hold Time 0 ns

t

h

Select Hold Time 10 ns

t

rec

Recovery Time 20 ns

CL = 15 pF

C

1.3 V

1.3 V 1.3 V

1.3 V

V

IN

V

OUT

t

PLH

t

PHL

1.3 V

1.3 V

V

IN

V

OUT

1.3 V

t

PLH

t

PHL

1.3 V

Figure 1 Figure 2

Figure 5

Figure 3 Figure 4

1.5 V 1.5 V

1.5 V

≈

1.5 V

1.5 V 1.5 V

1.5 V

≈

1.5 V

V

E

V

E

V

OUT

t

PZL

t

PLZ

V

OL

0.5 V

V

E

V

E

V

OUT

t

PZH

t

PHZ

0.5 V

≥

V

OH

3-STATE WAVEFORMS

AC LOAD CIRCUIT

SWITCH POSITIONS

SW2CL*

5 k

Ω

SW1

V

CC

R

L

TO OUTPUT

UNDER TEST

* Includes Jig and Probe Capacitance.

5-5

FAST AND LS TTL DATA

SN54/74LS323

SYMBOL SW1 SW2

t

PZH

Open Closed

t

PZL

Closed Open

t

PLZ

Closed Closed

t

PHZ

Closed Closed