SDFS069A – D2932, MARCH 1987 – REVISED OCTOBER 1993
• Full-Carry Look-Ahead Across the
Four Bits
• Systems Achieve Partial Look-Ahead
Performance With the Economy of Ripple
Carry
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
The ′F283 is a full adder that performs the addition
of two 4-bit binary words. The sum (Σ) outputs are
provided for each bit and the resultant carry (C4)
output is obtained from the fourth bit.
The device features full internal look-ahead
across all four bits generating the carry term C4 in
typically 5.7 ns. This capability provides the
system designer with partial look-ahead
performance at the economy and reduced
package count of a ripple-carry implementation.
The adder logic, including the carry, is
implemented in its true form. End-around carry
can be accomplished without the need for logic or
level inversion.
The ′F283 can be used with either all-active-high
(positive logic) or all-active-low (negative logic)
operands.
SN54F283 ...J PACKAGE
SN74F283 ...D OR N PACKAGE
SN54F283 . . . FK PACKAGE
A2
Σ1
NC
A1
B1
NC – No internal connection
(TOP VIEW)
Σ2
B2
A2
Σ1
A1
B1
C0
GND
(TOP VIEW)
B2ΣNC
3212019
4
5
6
7
8
910111213
C0
1
2
3
4
5
6
7
8
2
GND
16
15
14
13
12
11
10
NC
V
CC
B3
A3
Σ3
A4
B4
Σ4
C4
9
CC
V
B3
A3
18
Σ3
17
NC
16
A4
15
B4
14
4
C4
Σ
The SN54F283 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F283 is characterized for
operation from 0°C to 70°C.
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†
Σ
0
P
Σ
3
Q
CO
A1
A2
A3
A4
B1
B2
B3
B4
C0
5
3
14
12
6
2
15
11
7
0
3
0
3
CI
4
Σ1
1
Σ2
13
Σ3
10
Σ4
9
C4
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–1
Page 2
SN54F283, SN74F283
4-BIT BINARY FULL ADDERS
WITH FAST CARRY
SDFS069A – D2932, MARCH 1987 – REVISED OCT OBER 1993
logic diagram (positive logic)
11
B4
12
A4
10
9
C4
Σ4
15
B3
14
A3
2
B2
3
A2
6
B1
5
A1
7
C0
Pin numbers shown are for the D, J, and N packages.
13
Σ3
1
Σ2
4
Σ1
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
SN54F283, SN74F283
4-BIT BINARY FULL ADDERS
SDFS069A – D2932, MARCH 1987 – REVISED OCTOBER 1993
FUNCTION TABLE
OUTPUTS
INPUTS
A1B1A2B2Σ1Σ2C2Σ1Σ2C2
A3B3A4B4Σ3Σ4C4Σ3Σ4C4
LLLLLLLHLL
HLLLHLLLHL
LHLLHLLLHL
HHLLLHLHHL
LLHLLHLHHL
HLHLHHLLLH
LHHLHHLLLH
HHHLLLHHLH
LLLHLHLHHL
HLLHHHLLLH
LHLHHHLLLH
HHLHLLHHLH
LLHHLLHHLH
HLHHHLHLHH
LHHHHLHLHH
HHHHLHHHHH
NOTE: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs Σ1
and Σ2 and the value of the internal carry C2. The values at C2, A3, B3, A4,
and B4 are then used to determine outputs Σ3, Σ4, and C4.
WHEN C0 = LWHEN C0 = H
WHEN C2 = LWHEN C2 = H
WITH FAST CARRY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
§
NOTE 2: Load circuits and waveforms are shown in Section 1.
PHL
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
TO
OUTPUT
RL = 500 Ω,
TA = 25°C
′F283SN54F283SN74F283
MINTYPMAXMINMAXMINMAX
2.76.69.52.7142.710.5
3.26.69.53.2143.210.5
3.26.69.53.2143.210.5
2.76.69.52.7142.710.5
2.75.37.52.710.52.78.5
2.2572.2102.28
2.75.37.52.710.52.78.5
2.24.972.2102.28
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
§
UNIT
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1998, Texas Instruments Incorporated
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