Datasheet SN54ACT7811GB Datasheet (Texas Instruments)

SN54ACT7811

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

D

Member of the Texas Instruments

Widebus

D

Independent Asynchronous Inputs and

 Family

Outputs

D

1024 Words × 18 Bits

D

Read and Write Operations Can Be
Synchronized to Independent System
Clocks

D

Programmable Almost-Full/Almost-Empty
Flag

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ACT781 1 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data
at rates up to 28.5 MHz and access times of 20 ns in a bit-parallel format. Data outputs are noninverting with
respect to the data inputs. Expansion is easily accomplished in both word width and word depth.

The SN54ACT781 1 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry
adds the ability to synchronize independent read and write (interrupts, requests) to their respective system
clock.

D

Input-Ready, Output-Ready, and Half-Full
Flags

D

Cascadable in Word Width and/or Word
Depth

D

Fast Access Times of 20 ns With a 50-pF
Load

D

High Output Drive for Direct Bus Interface

D

Package Options Include 68-Pin Ceramic
PGA (GB) or Space-Saving 68-Pin Ceramic
Quad Flatpack (HV)

†

1024 × 18

The SN54ACT7811 is characterized for operation from –55°C to 125°C.

GB PACKAGE

(TOP VIEW)

123456789

A
B
C
D
E

F
G
H

J

†

The SN54ACT781 1 HV is not production released.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

GB-Package Terminal Assignments

TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME

A1 Q15 B7 Q5 F2 D17 H8 D0
A2 Q13 B8 Q4 F8 WRTEN2 H9 DAF
A3 Q12 B9 Q1 F9 AF/AE J1 D11
A4 Q11 C1 RESET G1 D16 J2 D10
A5 Q10 C2 Q16 G2 D15 J3 D8
A6 Q8 C8 Q2 G8 WRTCLK J4 NC
A7 Q7 C9 Q0 G9 WRTEN1 J5 D7
A8 Q6 D1 OE H1 D14 J6 D6
A9 Q3 D9 HF H2 D13 J7 D5
B1 OR E1 RDEN1 H3 D12 J8 D3
B2 Q17 E2 RDEN2 H4 D9 J9 D2
B3 Q14 E9 IR H6 D4
B5 Q9 F1 RDCLK H7 D1

VCC = B4, C6, C7, D2, D7, E8, G3, G4, G6 GND = B6, C3, C4, D3, D8, F3, F7, G7, H5
NC = No internal connection

D14
D13
D12

D1 1

D10

D9

V

CC

D8

GND

D7
D6
D5
D4
D3
D2
D1
D0

HV PACKAGE

(TOP VIEW)

D17

GND

RDCLK

RDEN1

D15

D16

87 65493

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27

28 29

31 32 33 34

30

RDEN2OERESET

†

CC

V

GND

OR

168672

35 36 37 38 39

66 65

CC

Q17

Q16

V

64 63 62 61

40 41 42 43

GND

Q15

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

V

CC

Q14
Q13
GND
Q12
Q11
V

CC

Q10
Q9
GND
Q8
Q7
V

CC

Q6
Q5
GND
Q4

IR

HF

Q0

Q1

Q2

CC

V

WRTEN1

WRTEN2

CC

V

GND

AF/AE

DAF

GND

WRTCLK

†

The SN54ACT781 1 HV is not production released.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GND

Q3

CC

V

SN54ACT7811

1024 × 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

logic symbol

†

WRTCLK

WRTEN1
WRTEN2

RESET

RDCLK

RDEN1

OE

RDEN2

DAF

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17

C1
G8
G9
F8
F1
E1

D1
E2
H9

H8
H7
J9
J8
H6
J7
J6
J5
J3

H4
J2
J1
H3
H2
H1
G2
G1
F2

FIFO 1024 × 18

RESET

WRTCLK

&

WRTEN

RDCLK

&

EN1

DEF ALMOST FULL

0

17

ALMOST FULL/EMPTY

RDEN

Data

Φ

HALF FULL

Data

IN RDY

OUT RDY

1

17

E9

IR

D9

HF

F9

AF/AE

B1

OR

C9

0

B9
C8
A9
B8
B7
A8
A7
A6
B5
A5
A4
A3
A2
B3
A1
C2
B2

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the GB package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

functional block diagram

OE

D0 – D17

RDCLK

RDEN1
RDEN2

WRTCLK

WRTEN1
WRTEN2

RESET

DAF

Synchronous

Read

Control

Synchronous

Write

Control

Reset

Logic

Read

Pointer

Write

Pointer

Status-

Flag

Logic

Location 1
Location 2

1024 × 18 RAM

Location 1023
Location 1024

Register

Q0 – Q17

OR
IR

HF
AF/AE

4

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I/O

DESCRIPTION

AF/AE

F9

O

TERMINAL

NAME NO.

DAF H9 I

D0–D17

HF D9 O

IR E9 O

OE D1 I

OR B1 O

Q0–Q17

RDCLK F1 I

RDEN1,

RDEN2

RESET C1 I

†

Terminals listed are for the GB package.

†

F2, G1, G2,

H1–H4, H6–H8,

J1–J3, J5–J9

A1–A9, B2, B3,
B5, B7–B9, C2,

C8, C9

E1
E2

SN54ACT7811

1024 × 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

Terminal Functions

AF/AE boundary is defined by the AF/AE offset value (X). This value can be programmed during
reset, or the default value of 256 can be used. The AF/AE flag is high when the FIFO contains (X + 1)
or fewer words or (1025 – X) or more words. The AF/AE flag is low when the FIFO contains between
(X + 2) and (1024 - X) words.
Programming procedure for AF/AE – The AF/AE flag is programmed during each reset cycle. The
AF/AE offset value (X) is either a user-defined value or the default of X = 256. Instructions to program
AF/AE using both methods are as follows:

User-defined X
Step 1:
Step 2:
Step 3:
Step 4:
Default X
T o redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset

cycle.

Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the
AF/AE offset value (X). With DAF
flag using X.

Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0–D8 also carry the AF/AE

I

offset value (X) on a high-to-low transition of the DAF
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512

or fewer words.
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR

is driven low on the rising edge of the second write clock (WRTCLK) pulse. IR is then driven high on
the rising edge of the second WRTCLK pulse after RESET
is driven low, IR is driven high on the second WRTCLK pulse after the first valid read.

Output enable. The data-out (Q0–Q17) outputs are in the high-impedance state when OE is low. OE
must be high before the rising edge of read clock (RDCLK) to read a word from memory.

Output ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR
is set low on the rising edge of the third read clock (RDCLK) pulse. OR is set high on the rising edge
of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the
rising edge of the first RDCLK pulse after the last word is read.

Data outputs. The first data word to be loaded into the FIFO is moved to the data-out (Q0–Q17)
register on the rising edge of the third read clock (RDCLK) pulse to occur after the first valid write.

O

The read-enable (RDEN1, RDEN2) inputs do not affect this operation. The following data is unloaded
on the rising edge of RDCLK when RDEN1, RDEN2, OE, and OR are high.

Read clock. Data is read out of memory on a low-to-high transition at RDCLK if the OR output and
the OE, RDEN1, and RDEN2 control inputs are high. RDCLK is a free-running clock and functions
as the synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.

Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out

I

of memory. The read enables are not used to read the first word stored in memory.
Reset. A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and

WRTCLK cycles. This ensures that the internal read and write pointers are reset and that OR, HF,
and IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF
level, a low pulse on RESET
previously stored. With DAF
default value of X = 256.

Take DAF
If the reset (RESET) input is not already low, take RESET low.
With DAF held low, take RESET high. This defines the AF/AE flag using X.
To retain the current offset for the next reset, keep DAF low.

from high to low.

held low, a low pulse on the reset (RESET) input defines the AF/AE

input.

goes high. After the FIFO is filled and IR

input at a low

defines AF/AE using the AF/AE offset value (X), where X is the value

at a high level, a low-level pulse on RESET defines AF/AE using the

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54ACT7811

I/O

DESCRIPTION

ОООООООО

1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

Terminal Functions (Continued)

TERMINAL

NAME NO.

WRTCLK G8 I

WRTEN1,

WRTEN2

†

Terminals listed are for the GB package.

RESET

†

G9
F8

Write clock. Data is written into memory on a low-to-high transition of WRTCLK if the IR output and
the WRTEN1 and WRTEN2 control inputs are high. WRTCLK is a free-running clock and functions
as the synchronizing clock for all data transfers into the FIFO. IR output is also driven synchronously
with respect to the WRTCLK signal.

Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word

I

to be written into memory. The write enables do not af fect the storage of the AF/AE offset value (X).

DAF

WRTCLK

WRTEN1

WRTEN2

D0 – D17

RDCLK

RDEN1

RDEN2

OE

Q0 – Q17

OR

Don’t Care

12341

Don’t Care

Don’t Care

Don’t Care

1234

Don’t Care

Don’t Care

Don’t Care

X

Invalid

2

†

1
0

AF/AE

HF

IR

†

X is the binary value of D0–D8 only.

6

Don’t Care

Don’t Care

Don’t Care

Store the Value of D0–D8 as X

Figure 1. Reset Cycle: Define AF/AE Using the Value of X

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Define the AF/AE Flag
Using the Value of X

SN54ACT7811

1024 × 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

RESET

DAF

WRTCLK

WRTEN1

WRTEN2

D0 – D17

RDCLK

RDEN1

RDEN2

OE

Q0 – Q17

OR

Don’t Care

12341

Don’t Care

Don’t Care

Don’t Care

1234

Don’t Care

Don’t Care

Invalid

Don’t Care

2

1
0

AF/AE

HF

IR

Don’t Care

Don’t Care

Don’t Care

Define the AF/AE Flag
Using the Value of X = 256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

RESET

DAF

WRTCLK

WRTEN1

WRTEN2

D0–D17

RDCLK

RDEN1

1
0

Don’t Care

1
0

W1 W2 W3 W4 W(X+2) W513 W(1025–X) W1025

123

1
0

RDEN2

OE

Q0–Q17

OR

AF/AE

HF

IR

Invalid

1
0

W1

Figure 3. Write Cycle

8

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ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

ООООООООООООООООООООООООООООО

SN54ACT7811

1024 × 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

RESET

DAF

WRTCLK

WRTEN1

WRTEN2

D0–D17

RDCLK

RDEN1

W1025

1
0

Don’t Care

1

2

RDEN2

OE

Q0–Q17

OR

AF/AE

HF

IR

W1 W2 W3 W(X+1) W(X+2) W513 W(1024–X) W(1025–X) W1024 W1025

W1

W514

Figure 4. Read Cycle

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

SN54ACT7811

I

§

1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage, V

I

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

stg

A

–55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN MAX UNIT

V
V
V
I

OH

I

OL

T

CC
IH
IL

A

Supply voltage 4.5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –8 mA
Low-level output current 16 mA
Operating free-air temperature –55 125 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

V

OH

V

OL

I

I

I

OZ

CC

C

i

C

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

ICC tested with outputs open

o

VCC = 4.5 V, IOH = – 8 mA 2.4 V
VCC = 4.5 V, IOL = 16 mA 0.5 V
VCC = 5.5 V, VI = VCC or 0 V ±5 µA
VCC = 5.5 V, VO = VCC or 0 V ±5 µA
VI = VCC – 0.2 V or 0 V 400 µA
One input at 3.4 V , Other inputs at VCC or GND 1 mA
VI = 0 V, f = 1 MHz 4 pF
VO = 0 V, f = 1 MHz 8 pF

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

twPulse duration

ns

timing requirements (see Figures 1 through 8)

f

Clock frequency 28.5 MHz

clock

Data in (D0–D17) high or low 14
WRTCLK high 10
WRTCLK low 14
RDCLK high 10
RDCLK low 14
DAF high 10
WRTEN1, WRTEN2 high or low 10
OE, RDEN1, RDEN2 high or low 10
Data in (D0–D17) before WRTCLK↑ 5
WRTEN1, WRTEN2 high before WRTCLK↑ 5
OE, RDEN1, RDEN2 high before RDCLK↑ 5

t

Setup time

su

t

Hold time

h

†

To permit the clock pulse to be utilized for reset purposes

Reset: RESET
Define AF/AE: D0–D8 before DAF↓ 5
Define AF/AE: DAF↓ before RESET↑ 7
Define AF/AE (default): DAF high before RESET↑ 5
Data in (D0–D17) after WRTCLK↑ 1
WRTEN1, WRTEN2 high after WRTCLK↑ 1
OE, RDEN1, RDEN2 high after RDCLK↑ 1
Reset: RESET
Define AF/AE: D0–D8 after DAF↓ 1
Define AF/AE: DAF low after RESET↑ 0
Define AF/AE (default): DAF high after RESET↑ 1

low before first WRTCLK and RDCLK↑

low after fourth WRTCLK and RDCLK↑

SN54ACT7811

1024 × 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

MIN MAX UNIT

†

†

7

0

ns

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

SN54ACT7811

RDCLK↑

Any Q

ns

t

AF/AE

ns

HF

ns

RESET↓

ns

OE

Any Q

ns

1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

switching characteristics over recommended operating free-air temperature range (see Figures 9
and 10)

VCC = 4.5 V to 5.5 V,

PARAMETER

f

max

t

pd

†

t

pd

t

pd

t

pd

pd

t

PLH

t

PHL

t

PLH

t

PHL

t

en

t

dis

†

This parameter is measured with CL = 30 pF (see Figure 5).

FROM

(INPUT)

WRTCLK or RDCLK 28.5 MHz

WRTCLK↑ IR 1 14 ns

RDCLK↑ OR 1 14 ns

WRTCLK↑

RDCLK↑

WRTCLK↑

RDCLK↑

TO

(OUTPUT)

AF/AE 2 23

HF 3 25

CL = 50 pF,
RL = 500 Ω,
TA = –55°C to 125°C

MIN MAX

3 20

5 24
5 24
5 23
5 23

1 11
1 14

UNIT

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

pd

Power dissipation capacitance per 1K bits CL = 50 pF, f = 5 MHz 65 pF

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2Figure 3Figure 4

TYPICAL PROPAGATION DELAY TIME

18

17

16

VCC = 5 V
TA = 25°C
RL = 500 Ω

LOAD CAPACITANCE

vs

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

TYPICAL CHARACTERISTICS

TYPICAL POWER DISSIPATION CAPACITANCE

68

fi = 5 MHz
TA = 25°C

67

CL = 50 pF

SN54ACT7811

1024 × 18

vs

SUPPLY VOLTAGE

15

14

13

12

pd

t – Propagation Delay Time – ns

11

10

0 50 100 150 200 250 300

C – Load Capacitance – pF

L

66

65

64

– Power Dissipation Capacitance – pF

63

pd

62

4.5 4.6 4.7 4.8 4.9 5 5.1

Figure 5 Figure 6

calculating power dissipation

The maximum power dissipation (PT) of the SN54ACT7811 can be calculated by:

P

= VCC × [ICC + (N × ∆ICC × dc)] + Σ (Cpd × V

T

Where:

I

= power-down ICC maximum

CC

N = number of inputs driven by a TTL device
∆ I

= increase in supply current

CC

dc = duty cycle of inputs at a TTL high level of 3.4 V
C
C
f
f

= power dissipation capacitance

pd

= output capacitive load

L

= data input frequency

i

= data output frequency

o

2

× fi) + Σ (CL × V

CC

5.2 5.3 5.4 5.5

VCC – Supply Voltage – V

2

× fo)

CC

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13

SN54ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

APPLICATION INFORMATION

expanding the SN54ACT7811

The SN54ACT7811 is expandable in width and depth. Expanding in word depth offers special timing
considerations:

– After the first data word is loaded into the FIFO, the word is unloaded, and the OR output goes high after

(N × 3) RDCLK cycles, where N is the number of devices used in depth expansion.

– After the FIFO is filled, the IR output goes low, the first word is unloaded, and the IR is driven high after (N

× 2) write clock cycles, where N is the number of devices used in depth expansion.

CLOCK

WRTCLK

WRTEN1
WRTEN2

IR

WRTCLK

WRTEN

D18 – D35

SN54ACT7811 SN54ACT7811

WRTCLK
WRTEN1
WRTEN2
IR

D0 – D17D0 – D17

RDCLK

OR

RDEN1

RDEN2

OE

Q0 – Q17

5 V

WRTCLK
WRTEN1
WRTEN2
IR

D0 – D17

RDCLK

RDEN2

OR
OE

Q0 – Q17

RDCLK
RDEN1RDEN1
RDEN2
OR
OE

Q0 – Q17

Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2

SN54ACT7811

WRTCLK
WRTEN1
WRTEN2
IR

D0 – D17

IR

SN54ACT7811

WRTCLK
WRTEN1
WRTEN2
IR

RDCLK

RDEN1
RDEN2

OR
OE

Q0 – Q17

RDCLK

RDEN1
RDEN2

OR

OE

RDCLK
RDEN

OE

Q18 – Q35

OR

14

D0 – D17

D0 – D17

Q0 – Q17

Figure 8. Word-Width Expansion: 1024 Words × 36 Bits

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Q0 – Q17

t

500 Ω

50 pF

t

500 Ω

50 pF

From Output

PARAMETER MEASUREMENT INFORMATION

Under Test

RL = 500 Ω CL = 50 pF

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SGAS001B – FEBRUARY 1995 – REVISED MARCH 1996

Input 1.5 V

t

pd

Output

SN54ACT7811

1024 × 18

3 V

0 V

t

pd

3 V

1.5 V
0 V

From Output

Under Test

LOAD CIRCUIT

S1

C

L

LOAD CIRCUIT

7 V

R1

Figure 9. Standard CMOS Outputs

RL = R1 = R2

R2

PARAMETER R1, R2 C

en

dis

t

pd

†

Includes probe and test fixture capacitanceFigure 9

Test
Point

t

PZH

t

PZL

t

PHZ

t

PLZ

TOTEM-POLE OUTPUTS

Input

t

PZL

Output

t

PZH

Output

†

L

p

p

500 Ω 50 pF Open

S1

Open

Closed

Open

Closed

1.5 V 1.5 V

t

PLZ

1.5 V

t

PHZ

1.5 V

VOLTAGE WAVEFORMS

0.3 V

3 V

0 V

≈ 3.5 V

V

0.3 V
V

≈ 0 V

OL

OH

Figure 10. 3-State Outputs (Any Q)

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15

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