Datasheet SMS8198S2.7, SMS8198SA, SMS8198SB Datasheet (SUMMIT)

SUMMIT

MICROELECTRONICS, Inc.

Philips TriMedia™ Processor Companion Supervisor
With a 16K-bit 2-wire Serial Memory

SMS8198

FEATURES

• Designed to operate with the Philips
TriMedia Processor

• Coordinating the System Reset Function and
Providing the Processor’s Configuration
Memory

• Multiple V

Thresholds

TRIP

- No External Components Required

• Guaranteed Reset Assertion to V

CC

-1V

• Reset is an I/O

- Allows System Reset Clean up

- Provides a De-bounced Manual Reset Func-

tion

• Industry Standard 2-wire Serial Interface

• Hardware Write Lockout Function

• High Reliability

- Endurance: 100,000 write cycles

- Data Retention: 100 Years

OVERVIEW

The SMS8198 is a precision supervisory circuit designed
specifically as a companion chip for the Philips TriMedia

Processor family. The SMS8198 monitors the power
supply and holds the system in reset whenever VCC is

below the V

threshold.

TRIP

In addition to the supervisory function, the SMS8198 has
16K-bits of nonvolatile memory that is used by the
TriMedia processor as the boot memory.

The SMS8198 provides 16K-bits of memory that is acces­sible through the industry standard 2-wire serial interface.
By integrating a precision supervisory circuit and the
hardware WP input, the SMS8198 becomes the perfect
companion chip for the Philips TriMedia processor family.
Its functions are integral to the boot hardware operation of
the TriMedia processors.

BLOCK DIAGRAM

V

CC

8

SCL

6

SDA

5

4

GND

1.26V

NONVOLATILE

MEMORY

ARRAY

WRITE

CONTROL

PROGRAMMABLE

RESET PULSE

GENERATOR

+

–

V

TRIP

RESET

CONTROL

2036 T BD 2.0

WP

7

TRI_RESET#

2

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone [phone] • Fax [phone] • www.summitmicro.com

© SUMMIT MICROELECTRONICS, Inc. 2000
2036 5.0 4/18/00

1

Characteristics subject to change without notice

10K

WP

4.7K

4.7K

4.7K

AudioCamera

Tri

Media

Processor

SMS8198

VCR/Monitor

TRI_RESET#

SCL
SDA

SMS8198

PCI_RESET#

TRI_RESET#

System Boot

Local Reset

PCI Bus

Figure 1. Typical Implementation of the SMS8198 and TriMedia Processor

The boot hardware operation begins with the assertion of
the reset signal TRI_RESET#. The TRI_RESET# output

from the SMS8198 is guaranteed to be valid at VCC -1.0V.
The reset output is asserted whenever VCC is less than the

V

threshold and will remain asserted after VCC is

TRIP

>V

for the duration of t

TRIP

. Whenever the

PURST

TRI_RESET# is active the memory will be write protected.
In addition to the reset write protection feature, pin 7 can

be tied to a pull-up to disable the write function of the
memory. This effectively turns the memory array into an
inexpensive boot ROM.

Audio

Block

Peripheral Peripheral

2036 ILL16.0

After reset is de-asserted, only the system boot block is
allowed to operate. At this point the TriMedia processor

takes over and begins to download data from the memory
array into its system boot block. The data downloaded

contains configuration data to set up the TriMedia proces­sor and to load special ID information into the PCI configu-

ration space register. The ID information is published in
the PCI configuration register to provide the 16 bit Sub­system ID and Subsystem Vendor ID.

It should be noted that both the threshold and the t
pulse width are programmable. Not only does this provide
maximum flexibility to the designer, but, as the processor
operating voltage levels migrate downwards, the
SMS8198 can be programmed to following this downward
trend. The values can be selected from the ordering
information table and the devices specified as standard
off-the-shelf items.

PURST

2036 5.0 4/18/00

2

V

CC

TRI_RESET#

V

RVALID

V

TRIP

t

GLITCH

t

PURST

Figure 2. Reset Output Timing

t

RPD

t

PURST

SMS8198

t

RPD

2036 T fig02 2.0

RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS

TA = -40°C to +85°C

Symbol Parameter Part no. Suffix Min. Typ. Max. Unit

V

TRIP

Reset Trip Point A (or) Blank 4.250 4.375 4.5 V

B 4.50 4.625 4.75 V

2.7 2.55 2.65 2.75 V

t

PURST

t

RPD

V

RVALID

t

GLITCH

V

OLRS

V

OHRS

Reset Timeout 200 ms
V

to RESET Output Delay 5 µs

TRIP

RESET Output Valid to VCC min. Guarantee 1 V
Glitch Reject Pulse Width note 1 30 ns
RESET Output Low Voltage IOL = 1mA 0.4 V
RESET High Voltage Output IOH = 800µA

3

2036 5.0 4/18/00

SMS8198

PIN CONFIGURATIONS

NC

TRI_RESET#

NC

GND

PIN NAMES

SDA Serial Data I/O

SCL Serial Clock Input

TRI_RESET# Reset Output

GND Ground

V

CC

WP Write Protect

NC No Connect

8-Pin SOIC

1
2
3
4

8
7
6
5

2036 T PCon 2.0

Supply Voltage

V

CC

WP
SCL
SDA

TRI_RESET# - is an active low open drain output. It is

driven low whenever VCC is below V

. TRI_RESET# is

TRIP

also an input and can be used to debounce a switch input
or perform signal conditioning. The TRI_RESET# pin

does have an internal pull-up and should be left uncon­nected if the signal is not used in the system. However,

when the pin is tied to a system TRI_RESET# line an
external pull-up resistor should be employed.

Write Protect (WP) - All write operations can be disabled
by maintaining WP > VIH.

No Connects (NC) - The no connect inputs are unused by
the SMS8198; however, to insure proper operation they
can be unconnected or tied to ground. They must not be
tied to VCC.

ENDURANCE AND DATA RETENTION

The SMS8198 is designed for applications requiring up to
100,000 erase/write cycles and unlimited read cycles. It

provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000

erase/write cycles.

RESET CONTROLLER DESCRIPTION

The device provides a precise reset output to a
microcontroller and it’s associated circuitry ensuring cor­rect system operation during power-up/down conditions
and brownout situations. The output is open drain, allow­ing control of the reset function by multiple devices.

PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data

into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.

Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire­ORed with any number of open-drain or open-collector
outputs.

During power-up the reset output remains in a fixed active
state until VCC passes through the reset threshold and

remains above the threshold for t
is valid whenever VCC is equal to or greater than 1V. If V

falls below the threshold for more than t

. The reset output

PURST

GLITCH

CC

the device

will immediately generate a reset and drive the output.
The reset pin is an I/O; therefore, forcing the pin to the

active state can also manually reset the device. Because
the I/O needs to be an open drain, the internal timer can
only be triggered by the leading edge of the input. The

resulting reset output will either be t

, or the externally

PURST

applied reset signal, whichever is longer. This can provide
an affective debounce or reset signal extender solution.

2036 5.0 4/18/00

4

SMS8198

SCL

SDA In

SCL from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start
Condition

Data must

remain stable

while clock

is HIGH.

Figure 3. Input Data Protocol

1

t

HD:DAT

Change

of data

allowed

t

SU:DAT

Data must

remain stable

while clock

is HIGH.

8

t

HD:DAT

t

AA

2036 ILL4.0

9

ACKnowledge

t

AA

Figure 4. Acknowledge Response From Receiver

2036 ILL6.0

5

2036 5.0 4/18/00

SMS8198

CHARACTERISTICS OF THE I2C BUS

General Description

The I2C bus was designed for two-way, two-line serial
communication between different integrated circuits. The
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus. Data transfer between devices may be initiated with
a START condition only when SCL and SDA are HIGH
(bus is not busy).

Input Data Protocol

One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition (See
Figure 2).

START and STOP Conditions

When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the “START”
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the “STOP” condi­tion (See Figure 3).

DEVICE OPERATION

The SMS8198 is a 16,384-bit serial E

2

PROM. The device
supports the I2C bidirectional data transmission protocol.
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device which receives data
as a “receiver.” The device controlling data transmission
is called the “master” and the controlled device is called
the “slave.” In all cases, the SMS8198 will be a “slave”
device, since it never initiates any data transfers.

ting eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to ACKnowledge that it received the
eight bits of data (See Figure 4).

The SMS8198 will respond with an ACKnowledge after
recognition of a START condition and its slave address

byte. If both the device and a write operation are selected,
the SMS8198 will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word.

In the READ mode, the SMS8198 transmits eight bits of
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
SMS8198 will continue to transmit data. If an
ACKnowledge is not detected, the SMS8198 will terminate
further data transmissions and awaits a STOP condition
before returning to the standby power mode.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier

(see figure 5). For the SMS8198 this is fixed as 1010

bin

Word Address

The next three bits of the slave address are an extension
of the array’s address and are concatenated with the eight
bits of address in the word address field, providing direct
access to the 2,048 X 8 array.

Read/Write Bit

The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.

.

Acknowledge (ACK)

Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-

2036 5.0 4/18/00

DEVICE

IDENTIFIER

1 0 1 0

Figure 5. Slave Address Byte

6

HIGH ORDER

WORD ADDRESS

A10 A9 A8 R/W

2036 ILL7.0

SMS8198

WRITE OPERATIONS

The SMS8198 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (tWR). The
page write operation allows up to 16 bytes in the same
page to be written during tWR.

Byte WRITE

After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 2,048
words in the array.

Upon receipt of the word address, the SMS8198 re­sponds with an ACKnowledge. After receiving the next
byte of data, it again responds with an ACKnowledge. The
master then terminates the transfer by generating a
STOP condition, at which time the SMS8198 begins the
internal write cycle.

While the internal write cycle is in progress, the SMS8198
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.

Page WRITE

The SMS8198 is capable of a 16-byte page write opera­tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the
SMS8198 will respond with an ACKnowledge.

The SMS8198 automatically increments the address for
subsequent data words. After the receipt of each word,
the four low order address bits are internally incremented
by one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad­dress counter will “roll over,” and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
transfer sequence.

SDA
Bus
Activity

Acknowledges Transmitted from

SMS8198 to Master Receiver

A
8

0= Write

A
C

W

K

0

S
T
A
R
T

1 0 1 0

Device

Type

Address

A10A9R

A10,A9,A8

Read/Write

Slave Address

Master Sends Read
Request to Slave

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

Shading Denotes

SMS8198

SDA Output Active

If single byte-write only,

Stop bit issued here.

Word Address Data Byte n Data Byte n+15

A7A6A5A4A3A2A1A0D7D5D6D

Master Writes Word
Address to Slave

Master Transmitter

to

Slave Receiver

A
C
K

Master Writes
Data to Slave

Master Transmitter

Slave Receiver

Slave Transmitter

to

Master Receiver

4

to

D3D2D

A

Data Byte n+1

C
K

D7D6D5D4D3D2D1D

D
0

1

Master Writes
Data to Slave

Master Transmitter

Slave Receiver

Slave Transmitter

to

Master Receiver

Acknowledges Transmitted from

SMS8198 to Master Receiver

A
C
K

D7D6D5D4D3D2D1D

0

Master Writes
Data to Slave

to

Slave Transmitter

Master Receiver

Master Transmitter

Slave Receiver

to

to

Slave Transmitter

Master Receiver

A

C

K

0

to

2036 ILL8.0

S
T
O
P

Figure 6. Page/Byte WRITE Mode

7

2036 5.0 4/18/00

SMS8198

Acknowledge Polling

When the SMS8198 is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.

To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 7).

Internal WRITE Cycle

In Progress;

Begin ACK Polling

Issue Start

Issue Slave

Address and

R/W = 0

ACK

Returned?

Next

operation a

WRITE?

Issue Byte

Address

No

Yes (Internal WRITE Cycle is completed)

No

Yes

Issue Stop

Issue Stop

READ OPERATIONS

Read operations are initiated with the R/W bit of the
identification field set to “1.” There are four different read
options:

1. Current Address Byte Read

2. Random Address Byte Read

3. Current Address Sequential Read

4. Random Address Sequential Read

Current Address Byte Read

The SMS8198 contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
SMS8198 receives the slave address field with the R/W
bit set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1.

The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the SMS8198 discontinues data transmission. See Fig­ure 8 for the address acknowledge and data transfer
sequence.

Proceed with

WRITE

Await Next

Command

2036 ILL9.0

Figure 7. Acknowledge Polling

SDA Bus Activity

S
T
A
R
T

Figure 8. Current Address Byte Read Mode

A9A

A

10RW

8

11100 1

Device

Type

Address

A10,A9,A8

Read/Write

1= Read

Slave Address

Master sends Read
request to Slave

Master Transmitter

to

Slave Receiver

A

Data Byte

C
K

D7D6D5D4D3D2D1D

Lack of ACK (low)
from Master
determines last
data byte to be read

Slave sends
Data to Master

Slave Transmitter

to

Master Receiver

1

0

S
T
O
P

Shading Denotes

SDA Output Active

SMS8198

2036 ILL10.0

2036 5.0 4/18/00

8

SMS8198

Random Address Byte Read

Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condi­tion and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
SMS8198 to the desired address.

SDA Bus
Activity

A10A9RWA

1010 1010 10

S

Device

T
A

Address

R
T

Type

A10,A9,A8

Read/Write

8

0= Write

A

C

Word Address

K

A7A6A5A4A3A2A1A

Slave Address

Master Transmitter

Slave Receiver

Shading Denotes

SMS8198

SDA Output Active

Master sends Read
request to Slave

to

Slave Transmitter

Master Receiver

Master Writes Word
Address to Slave

Master Transmitter

to

Slave Receiver

Slave Transmitter

to

Master Receiver

After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The SMS8198 will respond with an acknowl­edge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The SMS8198 discontinues data transmission
and reverts to its standby power mode. See Figure 9 for
the address, acknowledge and data transfer sequence.

A
C
K

0

S

Device

T

Type

A

Address

R
T

Slave Address

Master Requests
Data from Slave

Master Transmitter

Slave Receiver

to

A10A

A10,A9,A8

Read/Write

to

A

A9R

C

W

8

1= Read

Slave Transmitter

Master Receiver

Data Byte

K

D7D6D5D4D3D2D1D

Lack of ACK (low)
from Master
determines last
data byte to be read

Slave sends
Data to Master

Slave Transmitter

Master Receiver

to

to

0

2036 ILL11.0

1

S

T
O
P

Figure 9. Random Address Byte Read Mode

9

2036 5.0 4/18/00

Sequential READ

Sequential READs can be initiated as either a current
address READ or random access READ. The first word is
transmitted as with the other byte read modes (current
address byte READ or random address byte READ);
however, the master now responds with an ACKnowledge,
indicating that it requires additional data from the
SMS8198. The SMS8198 continues to output data for
each ACKnowledge received. The master terminates the
sequential READ operation by not responding with an
ACKnowledge, and issues a STOP conditions.

SMS8198

During a sequential read operation, the internal address
counter is automatically incremented with each acknowl­edge signal. For read operations, all address bits are
incremented, allowing the entire array to be read using a
single read command. After a count of the last memory
address, the address counter will ‘roll-over’ and the
memory will continue to output data. See Figure 10 for the
address, acknowledge and data transfer sequence.

SDA Bus
Activity

A10A9RWA

1010 1010 10

S
T

Device

A

Type

R

Address

T

A10,A9,A8

Read/Write

Master sends Read
request to Slave

Master Transmitter

to

Slave Receiver

Slave Transmitter

Shading Denotes

SDA Output Active

A

Word Address

C

8

K

A7A6A5A4A3A2A1A

0= Write

Master Writes Word
Address to Slave

Master Transmitter

Slave Receiver

to

Master Receiver

SMS8198

Acknowledges from SMS8198

A
C
K

0

S

T

Device

A
R

Address

T

Type

A

10

A10,A9,A80

Read/Write

Slave AddressSlave Address

Master Requests
Data from Slave

Master Transmitter

to

Slave Transmitter

to

Master Receiver

to

Slave Receiver

Slave Transmitter

A

A

A9R

8

1= Read

First Data Byte

C

W

K

D7D6D5D4D3D2D1D

Slave sends
Data to Master

Slave Transmitter

Master Receiver

to

Master Receiver

Acknowledge from

Master Receiver

A

C

K

0

to

Master Transmitter

to

Slave Receiver

Lack of

Acknowledge from

Master Receiver

Last Data Byte

D7D6D5D4D3D2D1D

Lack of ACK (low)
determines last
data byte to be read

Slave sends
Data to Master

Slave Transmitter

to

Master Receiver

0

2036 ILL12.0

1

S
T
O
P

2036 5.0 4/18/00

Figure 10. Sequential READ Operation (starting with a Random Address READ)

10

SMS8198

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ............................................................................................................... -40°C to +85°C

Storage Temperature ..................................................................................................................... -65°C to +125°C

Soldering Temperature (less than 10 seconds).............................................................................................. 300°C

Supply Voltage ........................................................................................................................................... 0 to 6.5V

Voltage on Any Pin...................................................................................................................... -0.3V to V

ESD Voltage (JEDEC method)...................................................................................................................... 2,000V

NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses
beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

SMS8198, TA = -40°C to +85°C, VCC = 2.7V to 5.5V

Symbol Parameter Conditions Min Max Units

I

CC

I

SB

I

LI

I

LO

V

IL

V

IH

V

OL

V

ROL

Supply Current (CMOS) SDA = Open

Standby Current (CMOS) SCL = SDA = V

Input Leakage VIN = 0 To V
Output Leakage V
Input Low Voltage S0, S1, S2, SCL, SDA, RESET 0.3xV
Input High Voltage S0, S1, S2, SCL, SDA 0.7xV
Output Low Voltage IOL = 3mA 0.4 V
RESET Low Output VCC = 1.0V, IOL = 100µA 0.3 V

SCL = CMOS Levels @ 100KHz V
All other inputs = GND or V

All other inputs = GND

= 0 To V

OUT

VCC = 2.7V, IOL = 400µA 0.3 V
VCC = 4.5V, IOL = 1mA 0.4 V

CC

CC

CC

CC

=5.5V 3 mA

CC

V

=3.3V 2 mA

CC

V

=5.5V 50

CC

V

=3.3V 25 µA

CC

CC

AC ELECTRICAL CHARACTERISTICS

SMS8198, TA = -40°C to +85°C, VCC = 2.7V to 5.5V

+0.3V

CC

µA

10 µA
10 µA

CC

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2036 5.0 4/18/00

CAPACITANCE

TA = 25°C, f = 100KHz

Symbol Parameter Max Units

SMS8198

t

R

SCL

t

SU:SDA

SDA In

SDA Out

C
C

IN

OUT

Input Capacitance 5 pF

Output Capacitance 8 pF

2036 PGM T3.0

t

t

F

t

HD:SDA

t

AA

HIGH

t

HD:DAT

t

LOW

t

DH

t

SU:DAT

t

SU:STO

t

BUF

2047 Fig07 1.0

Figure 11. Bus Timing

2036 5.0 4/18/00

12

ORDERING INFORMATION

SMS8198

Base Part Number

Package

S = 8 Lead SOIC

SMS8198

S

A

V

Threshold

TRIP

A or Blank = 4.5V
B = 4.75V

2.7 = 2.7V

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8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

.050 (1.27) TYP.

.157 (4.00)
.150 (3.80)

.275 (6.99) TYP.

SMS8198

.050 (1.270) TYP.
8 Places

.061 (1.75)
.053 (1.35)

.0192 (.49)
.0138 (.35)

1

.196 (5.00)
.189 (4.80)

.0098 (.25)
.004 (.127)

.05 (1.27) TYP.

FOOTPRINT

.035 (.90)
.016 (.40)

.020 (.50)
.010 (.25)

.244 (6.20)
.228 (5.80)

.030 (.762) TYP.
8 Places

x45°

8pn JEDEC SOIC ILL.2

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon
a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.
shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure
or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its
safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives
written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks;
and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.

I2C is a trademark of Philips Corporation.
© Copyright 2000 SUMMIT Microelectronics, Inc.

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