Datasheet SMJ626162-12, SMJ626162-14, SMJ626162-15, SMJ626162-20 Datasheet (AUSTIN)

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

Organization
512K × 16 Bits × 2 Banks

D

3.3-V Power Supply (±5% Tolerance)

D

Two Banks for On-Chip Interleaving
(Gapless Accesses)

D

High Bandwidth – Up to 83-MHz Data Rates

D

Read Latency Programmable to
2 or 3 Cycles From Column-Address Entry

D

Burst Sequence Programmable to Serial or
Interleave

D

Burst Length Programmable to 1, 2, 4, 8, or
256 (Full Page)

D

Chip Select and Clock Enable for Enhanced
System Interfacing

D

Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control

D

Autorefresh Capability

D

4K Refresh (Total for Both Banks)

D

High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface

D

Power-Down Mode

D

Pipeline Architecture

D

T emperature Ranges:

Operating, – 55°C to 125°C
Storage, – 65°C to 150°C

D

Performance Ranges:

SYNCHRONOUS ACCESS TIME REFRESH

CLOCK CYCLE CLOCK TO TIME

TIME OUTPUT INTERV AL

t

CK

t

AC

t

REF

(MIN)

{

(MIN)

{

(MAX)

’626162-12 12 ns 8ns 32ms
’626162-15 15 ns 9ns 32ms
’626162-20 20 ns 10ns 32ms

†

Read latency = 3

description

The SMJ626162 series of devices are
16777216-bit synchronous dynamic random­access memory (SDRAM) devices organized as
two banks of 524288 words with 16 bits per word.

All inputs and outputs of the SMJ626162 series
are compatible with the LVTTL interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PIN NOMENCLATURE

A[0:10] Address Inputs

A0–A10 Row Addresses
A0–A7 Column Addresses

A10 Automatic-Precharge Select
A11 Bank Select
CAS

Column-Address Strobe
CKE Clock Enable
CLK System Clock
CS

Chip Select
DQ[0:15] SDRAM Data Input/Data Output
DQML, DQMU Data-Input/Data-Output Mask Enable
NC No Connect
RAS

Row-Address Strobe
V

CC

Power Supply (3.3-V Typical)
V

CCQ

Power Supply for Output Drivers

(3.3-V Typical)
V

SS

Ground
V

SSQ

Ground for Output Drivers
W

Write Enable

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

V

SS

DQ15
DQ14
V

SSQ

DQ13
DQ12
V

CCQ

DQ11
DQ10
V

SSQ

DQ9
DQ8
V

CCQ

NC
DQMU
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

V

CC

DQ0
DQ1

V

SSQ

DQ2
DQ3

V

CCQ

DQ4
DQ5

V

SSQ

DQ6
DQ7

V

CCQ

DQML

W
CAS
RAS

CS
A11
A10

A0
A1
A2
A3

V

CC

HKD PACKAGE

(TOP VIEW)

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The SDRAM employs state-of-the-art technology for high performance, reliability , and low power requirements.
All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with
high-speed microprocessors and caches.

The SMJ626162 SDRAM is available in a 50-lead, 650-mil-wide ceramic dual flatpack (HKD suffix).

functional block diagram

CLK
CKE

CS

DQMx

RAS
CAS

W

A0–A11

AND

Control

Mode Register

Array Bank T

Array Bank B

DQ

Buffer

DQ0–DQ15

16

12

operation

All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ15, are also referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently; however, a bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.

Five basic commands or functions control most operations of the ’626162:

D

Bank-activate/row-address entry

D

Column-address entry/write operation

D

Column-address entry/read operation

D

Bank-deactivate

D

Autorefresh

Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.

T able 1, T able 2, and T able 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

Table 1. Basic Command Truth Table

†

COMMAND

STATE OF

BANK(S)

CS RAS CAS W A11 A10 A9–A0 MNEMONIC

Mode register set

T = deac
B = deac

L L L L X X

A9=V
A8 –A7 = 0
A6–A0 = V

MRS

Bank deactivate (precharge) X L L H L BS L X DEAC
Deactivate all banks X L L H L X H X DCAB
Bank activate/row-address entry SB = deac L L H H BS V V ACTV
Column-address entry/write operation SB = actv L H L L BS L V WRT
Column-address entry/write operation

with auto-deactivate

SB = actv L H L L BS H V WRT-P

Column-address entry/read operation SB = actv L H L H BS L V READ
Column-address entry/read operation

with auto-deactivate

SB = actv L H L H BS H V READ-P

No operation X L H H H X X X NOOP
Control-input inhibit/no operation X H X X X X X X DESL

Autorefresh

‡

T = deac
B = deac

L L L H X X X REFR

†

For execution of these commands on cycle n, one of the following must be true:
– CKE (n–1) must be high
– t

CESP

must be satisfied for power-down exit

– t

CES

and n

CLE

must be satisfied for clock-suspend exit. DQMx (n) is irrelevant.

‡

Autorefresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.

Legend:

n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
V = Valid
T = Bank T
B = Bank B
actv = Activated
deac = Deactivated
BS = Logic high to select bank T; logic low to select bank B
SB = Bank selected by A11 at cycle n

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

Table 2. Clock-Enable (CKE) Command Truth Table

†

COMMAND STATE OF BANK(S)

CKE

(n–1)

CKE

(n)

CS
(n)

RAS

(n)

CAS

(n)

W

(n)

MNEMONIC

Power-down entry on cycle (n + 1)

‡

T = no access operation

§

B = no access operation

§

H L X X X X PDE

Power-down exit

¶

T = power down
B = power down

L H X X X X —

CLK suspend on cycle (n + 1)

T = access operation

§

B = access operation

§

H L X X X X HOLD

CLK suspend exit on cycle (n + 1)

T = access operation

§

B = access operation

§

L H X X X X —

†

For execution of these commands, A0–A1 1 (n) and DQMx (n) are don’t care entries.

‡

On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.

§

A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.

¶

If setup time from CKE high to the next CLK high satisfies t

CESP

, the device executes the respective command (listed in Table 1). Otherwise,

either a DESL or a NOOP command must be applied before any other command.

Legend:

n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
T = Bank T
B = Bank B

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

Table 3. Data Mask (DQM) Command Truth Table

†

COMMAND

STATE OF

BANK(S)

DQML

DQMU

‡

(n)

DATA IN

(n)

DATA OUT

(n + 2)

MNEMONIC

—

T = deac

and

B = deac

X N/A Hi-Z —

—

T = actv

and

B = actv

(no access operation)

§

X N/A Hi-Z —

Data-in enable

T = write

or

B = write

L V N/A ENBL

Data-in mask

T = write

or

B = write

H M N/A MASK

Data-out enable

T = read

or

B = read

L N/A V ENBL

Data-out mask

T = read

or

B = read

H N/A Hi-Z MASK

†

For execution of these commands on cycle n, one of the following must be true:
– CKE (n) must be high
– t

CESP

must be satisfied for power-down exit

– t

CES

and n

CLE

must be satisfied for clock-suspend exit.

CS

(n), RAS(n), CAS(n), W(n), and A0–A1 1 are irrelevant.

‡

DQML controls DQ0 –DQ7.
DQMU controls DQ8 –DQ15.

§

A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.

Legend:

n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
V = Valid
M = Masked input data
N/A = Not applicable
T = Bank T
B = Bank B
actv = Activated
deac = Deactivated
write = Activated and accepting data in on cycle n
read = Activated and delivering data out on cycle (n + 2)
Hi-Z = High-impedance state

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

6

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burst sequence

All data for the ’626162 is written or read in a burst fashion—that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first access can be at preceding, as well as succeeding, column
addresses, depending on the starting address entered. This sequence can be programmed to follow either a
serial burst or an interleave burst (see T able 4, T able 5, and T able 6). The length of the burst can be programmed
to be either 1, 2, 4, 8, or full-page (256) accesses (see the section on setting the mode register). After a read
burst is completed (as determined by the programmed burst length), the outputs are in the high-impedance state
until the next read access is initiated.

Table 4. 2-Bit Burst Sequences

INTERNAL COLUMN ADDRESS A0

DECIMAL BINARY

START 2ND START 2ND

0 1 0 1

Serial

1 0 1 0
0 1 0 1

Interleave

1 0 1 0

Table 5. 4-Bit Burst Sequences

INTERNAL COLUMN ADDRESS A1–A0

DECIMAL BINARY

START 2ND 3RD 4TH START 2ND 3RD 4TH

0 1 2 3 00 01 10 11
1 2 3 0 01 10 11 00

Serial

2 3 0 1 10 11 00 01
3 0 1 2 11 00 01 10
0 1 2 3 00 01 10 11
1 0 3 2 01 00 11 10

Interleave

2 3 0 1 10 11 00 01
3 2 1 0 11 10 01 00

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

burst sequence (continued)

Table 6. 8-Bit Burst Sequences

INTERNAL COLUMN ADDRESS A2–A0

DECIMAL BINARY

START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH

0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111
1 2 3 4 5 6 7 0 001 010 011 100 101 110 111 000
2 3 4 5 6 7 0 1 010 011 100 101 110 111 000 001
3 4 5 6 7 0 1 2 011 100 101 110 111 000 001 010

Serial

4 5 6 7 0 1 2 3 100 101 110 111 000 001 010 011
5 6 7 0 1 2 3 4 101 110 111 000 001 010 011 100
6 7 0 1 2 3 4 5 110 111 000 001 010 011 100 101
7 0 1 2 3 4 5 6 111 000 001 010 011 100 101 110
0 1 2 3 4 5 6 7 000 001 010 011 100 101 110 111
1 0 3 2 5 4 7 6 001 000 011 010 101 100 111 110
2 3 0 1 6 7 4 5 010 011 000 001 110 111 100 101
3 2 1 0 7 6 5 4 011 010 001 000 111 110 101 100

Interleave

4 5 6 7 0 1 2 3 100 101 110 111 000 001 010 011
5 4 7 6 1 0 3 2 101 100 111 110 001 000 011 010
6 7 4 5 2 3 0 1 110 111 100 101 010 011 000 001
7 6 5 4 3 2 1 0 111 110 101 100 011 010 001 000

latency

The beginning data-out cycle of a read burst can be programmed to occur 2 or 3 CLK cycles after the read
command (see the section on setting the mode register). This feature allows the adjustment of the ’626162 to
operate in accordance with the system’s capability to latch the data output from the ’626162. The delay between
the READ command and the beginning of the output burst is known as

read latency

(also known as CAS
latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening
gaps. Use of minimum read latencies is restricted, based on the particular maximum frequency rating of the
’626162.

There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the contents of the mode register.

two-bank operation

The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Then, each bank must be
deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry
command (ACTV) is entered by holding RAS

low, CAS high, W high, and A11 valid on the rising edge of CLK.
A bank can be deactivated either automatically during a READ-P or a WRT-P command or by use of the
deactivate-bank command (DEAC). Both banks can be deactivated at once by use of the DCAB command (see
Table 1 and the section on bank deactivation).

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

two-bank row-access operation

The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM. This is accomplished by activating one bank with a row address and, while the data
stream is being accessed to/from that bank, activating the second bank with another row address. When the
data stream to/from the first bank is complete, the data stream to/from the second bank can begin without
interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row
address for the next round of accesses. In this manner, operation can continue in an interleaved fashion.
Figure 25 is an example of two-bank, row-interleaving, read bursts with automatic deactivate for a read latency
of 3 and a burst length of 8.

two-bank column-access operation

The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A1 1 can be used to alternate
read or write commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 26 is an example of two-bank, column-interleaving, read bursts
for a read latency of 3 and a burst length of 2.

bank deactivation (precharge)

Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A1 1 is used to select the bank to be precharged as shown in T able 1.
A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is held high
during the entry of a read or write command, the accessed bank (selected by A1 1) is deactivated automatically
upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank
remains active following the burst. The read and write commands with automatic deactivation are denoted as
READ-P and WRT-P.

chip select (CS)

CS can be used to select or deselect the ’626162 for command entry, which might be required for
multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again. Device select is accomplished by holding
CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising
CLK edge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see T able 1
and T able 2). The use of CS

does not affect an access burst that is in progress; the DESL command can restrict

only RAS, CAS, and W input to the ’626162.

data mask

The mask command, or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any individual data cycle within a read burst or a write burst. DQML controls
DQ0–DQ7, and DQMU controls DQ8–DQ15. The application of DQMx to a write burst has no latency
(n

DID

= 0 cycle), but the application of DQMx to a read burst has a latency of n

DOD

= 2 cycles. During a write
burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst,
if DQMx is held high on the rising edge of CLK, then n

DOD

cycles after the rising edge of CLK, the data-output
will be in the high-impedance state. Figure 16, Figure 29, Figure 30, Figure 31, and Figure 32 show examples
of data-mask operations.

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

setting the mode register

The ’626162 contains a mode register that must be programmed with the read latency , the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on address lines A0–A9. A logic 0 must be entered on A7 and A8. A10 and A1 1 are don’t care entries
for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined
by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS

, CAS, and W low and the input-mode word
valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Reserved

0 = Serial
1 = Interleave

0 0

(burst type)

REGISTER

WRITE­BURST

REGISTER

BITS

†

READ

REGISTER

BITS

†

BIT A9

BURST

LENGTH

A6 A5 A4

LATENCY

‡

A2 A1 A0

BURST LENGTH

0
1

A2–A0

1

00110

1

2
3

0
0
0
0
1

0
0
1
1
1

0
1
0
1
1

1
2
4
8

256

†

All other combinations are reserved.

‡

See the timing requirements for minimum valid read latencies based on maximum frequency rating.

Figure 1. Mode-Register Programming

refresh

The ’626162 must be refreshed at intervals not exceeding t

REF

(see timing requirements) or data cannot be
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, or by
performing 4096 autorefresh (REFR) commands. Regardless of the method used, refresh must be
accomplished before t

REF

has expired.

autorefresh (REFR)

Before performing a REFR operation, both banks must be deactivated (placed in precharge). T o enter a REFR
command, RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, both banks of the ’626162 have
been refreshed. The external address and bank select (A1 1) are ignored. The execution of a REFR command
automatically deactivates both banks upon completion of the internal autorefresh cycle. This allows consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before t

REF

expires.

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CLK-suspend/power-down mode

For normal device operation, CKE must be held high to enable CLK. If CKE goes low during the execution of
a read or write operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current
state. No further inputs are accepted until CKE returns high; this is known as a CLK-suspend operation, and
its execution is denoted as a HOLD command. The device resumes operation from the point at which it was
placed in suspension, beginning with the second rising edge of CLK after CKE returns high.

If CKE is brought low when no read or write command is in progress, the device enters the power-down mode.
If both banks are deactivated when the power-down mode is entered, power consumption is reduced to the
minimum. Power-down mode can be used during row-active or autorefresh periods to reduce input-buffer
power. After power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that
data in the device remains valid, the power-down mode must be exited periodically to meet the requirements
described earlier for device refresh. When exiting power-down mode, new commands can be entered on the
first CLK edge after CKE returns high, provided that the setup time (t

CESP

) is satisfied. Table 2 shows the
command configuration for a CLK-suspend/power-down operation; Figure 17, Figure 18, and Figure 35 show
examples of the procedure.

interrupted bursts

A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of a READ-P or a
WRT-P operation is not supported.

Table 7. Read-Burst Interruption

INTERRUPTING

COMMAND

EFFECT OR NOTE ON USE DURING READ BURST

READ, READ-P

Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met
and new output cycles begin (see Figure 2).

WRT, WRT-P

The WRT (WRT -P) command immediately supersedes the read burst in progress. T o avoid data contention, DQMx must
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (n

CCD

–1), n

CCD

, and

(n

CCD

+1), assuming that there is any output on these cycles (see Figure 3).

DEAC, DCAB

The DQ bus is in the high-impedance state when n

HZP

cycles are satisfied or when the read burst completes, whichever

occurs first (see Figure 4).

CLK

DQ

READ Command

at Column Address C0

C0 C1 C1 + 1 C1 + 2

Interrupting

READ Command

at Column Address C1

n

CCD

= 1 Cycle

Output Burst for the

Interrupting READ

Command Begins Here

NOTE A: For this example, assume read latency = 3 and burst length = 4.

Figure 2. Read Burst Interrupted by Read Command

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

11

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupted bursts (continued)

CLK

DQ

READ Command

Interrupting

WRT Command

QD

D

DQMx

See Note B

n

CCD

= 5 Cycles

NOTES: A. For this example, assume read latency = 3 and burst length = 4.

B. DQMx must be high to mask output of the read burst on cycles (n

CCD

– 1), n

CCD

, and (n

CDD

+ 1).

Figure 3. Read Burst Interrupted by Write Command

DQ

CLK

QQ

Interrupting

DEAC/DCAB

Command

READ Command

n

HZP

n

CCD

= 2 Cycles

NOTE A: For this example, assume read latency = 3 and burst length = 4.

Figure 4. Read Burst Interrupted by DEAC Command

Table 8. Write-Burst Interruption

INTERRUPTING

COMMAND

EFFECT OR NOTE ON USE DURING WRITE BURST

READ, READ-P Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).
WRT, WRT-P

The new WRT (WRT -P) command and data inputs immediately supersede the write burst in progress
(see Figure 6).

DEAC, DCAB

The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
mask the DQ bus such that the write recovery specification (t

RWL

) is not violated by the

interrupt (see Figure 7).

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupted bursts (continued)

CLK

DQ

READ

Command

DQ

Q

n

CCD

= 1 Cycle

WRT

Command

Q

NOTE A: For this example, assume read latency = 3 and burst length = 4.

Figure 5. Write Burst Interrupted by Read Command

DQ

CLK

C1 + 3C1 + 2C1 + 1C1C0 + 1C0

n

CCD

= 2 Cycles

WRT Command

at Column

Address C0

Interrupting

WRT Command

at Column Address C1

NOTE A: For this example, assume burst length = 4.

Figure 6. Write Burst Interrupted by Write Command

CLK

DQ D D Ignored

n

CCD

= 3 Cycles

WRT Command

DQMx

t

RWL

Ignored

Interrupting

DEAC or DCAB

Command

NOTE A: For this example, assume burst length = 4.

Figure 7. Write Burst Interrupted by DEAC/DCAB Command

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

13

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

power up

Device initialization should be performed after a power up to the full VCC level; however, after power is
established, a 200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the
device must be deactivated. Eight REFR commands must be performed and the mode register must be set to
complete the device initialization.

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over ambient temperature range (unless otherwise noted)

†

Supply voltage range, VCC – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range for output drivers, V

CCQ

– 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any input pin (see Note 1) – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any output pin – 0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ambient temperature range, T

A

– 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

– 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 3.135 3.3 3.465 V

V

CCQ

Supply voltage for output drivers

‡

3.135 3.3 3.465 V

V

SS

Supply voltage 0 V

V

SSQ

Supply voltage for output drivers 0 V

V

IH

High-level input voltage 2 VCC + 0.3 V

V

IL

Low-level input voltage – 0.3 0.8 V

T

A

Ambient temperature –55 125 °C

‡

V

CCQ

v VCC + 0.3 V

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

15

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 2)

’626162-12 ’626162-15 ’626162-20

PARAMETER

TEST CONDITIONS

MIN MAX MIN MAX MIN MAX

UNIT

V

OH

High-level output
voltage

IOH = –2 mA 2.4 2.4 2.4 V

V

OL

Low-level output
voltage

IOL = 2 mA 0.4 0.4 0.4 V

I

I

Input current
(leakage)

0 V ≤ VI ≤ VCC,
All other pins = 0 V to V

CC

±10 ±10 ±10 µA

I

O

Output current
(leakage)

0 V ≤ VO ≤ V

CCQ

, Output disabled ±10 ±10 ±10 µA

Average read or

Burst length = 1,
tRC ≥ tRC MIN,

Read latency = 2 85 75 70

I

CC1

g

write current

IOH/I

OL

=

0 mA

,
One bank activated
(see Note 3)

Read latency = 3 100 95 85

mA

I

CC2P

Precharge standby

CKE ≤ VIL MAX, tCK = MIN (see Note 4) 2 2 2

I

CC2PS

gy

current in
power-down mode

CKE and CLK v VIL MAX,
tCK = ∞ (see Note 5)

2 2 2

mA

I

CC2N

Precharge standby

CKE ≥ VIH MIN, tCK = MIN (see Note 4) 40 35 30

I

CC2NS

current in
nonpower-down
mode

CKE ≥ VIH MIN, CLK ≤ VIL MAX,
tCK = ∞ (see Note 5)

2 2 2

mA

I

CC3P

Active standby

CKE ≤ VIL MAX, tCK = MIN
One bank activated (see Note 4)

10 10 10

I

CC3PS

current in
power-down mode

CKE and CLK ≤ VILMAX, tCK = ∞
One bank activated (see Note 5)

10 10 10

mA

I

CC3N

Active standby
current in

CKE ≥ VIH MIN, tCK = MIN
One bank activated (see Note 4)

55 45 40

I

CC3NS

nonpower-down
mode

CKE ≥ VIH MIN, CLK ≤ VIL MAX,
tCK = ∞, One bank activated (see Note 5)

15 15 15

mA

Continuous burst,
IOH/IOL = 0 mA,

Read latency = 2 165 130 110

I

CC4

Burst current

All banks activated

,

n

CCD

= one cycle

(see Note 6)

Read latency = 3 210 175 150

mA

Read latency = 2 120 100 80

I

CC5

Autorefresh

t

RC

≥

t

RC

MIN

Read latency = 3 120 100 80

mA

NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.

3. Control and address inputs change state twice during tRC.

4. Control and address inputs change state once every 2 × tCK.

5. Control and address inputs do not change state (stable).

6. Control and address inputs change state once every cycle.

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

16

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 7)

PARAMETER MIN MAX UNIT

C

i(S)

Input capacitance, CLK input 8 pF

C

i(AC)

Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W 8 pF

C

i(E)

Input capacitance, CKE input 8 pF

C

o

Output capacitance 10 pF

NOTE 7: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal

applied to the pin under test. All other pins are open.

ac timing requirements

†‡

’626162-12 ’626162-15 ’626162-20

MIN MAX MIN MAX MIN MAX

UNIT

Read latency = 2 15 20 30

tCKCycle time, CLK (system clock)

Read latency = 3 12 15 20

ns

t

CKH

Pulse duration, CLK (system clock) high 4 4 4 ns

t

CKL

Pulse duration, CLK (system clock) low 4 4 4 ns
Access time, CLK ↑ to data out

Read latency = 2 9 15 20

t

AC

,

(see Note 8)

Read latency = 3

8 9 10

ns

t

LZ

Delay time, CLK to DQ in the low-impedance state (see Note 9) 0 0 0 ns
Delay time, CLK to DQ in the

Read latency = 2 8 14 15

t

HZ

y,

high-impedance state (see Note 10)

Read latency = 3

8 11 12

ns

t

DS

Setup time, data input 3 4 4 ns

t

AS

Setup time, address 3 4 4 ns

t

CS

Setup time, control input (CS, RAS, CAS, W, DQMx) 3 4 4 ns

t

CES

Setup time, CKE (suspend entry/exit, power-down entry) 3 4 4 ns

t

CESP

Setup time, CKE (power-down/self-refresh exit) (see Note 11) 10 10 10 ns

t

OH

Hold time, CLK ↑ to data out 1.5 2 2 ns

t

DH

Hold time, data input 2 2 2 ns

t

AH

Hold time, address 2 2 2 ns

t

CH

Hold time, control input (CS, RAS, CAS, W, DQMx) 2 2 2 ns

t

CEH

Hold time, CKE 2 2 2 ns

t

RC

REFR command to ACTV , MRS, or REFR command;
ACTV command to ACTV , MRS, or REFR command

96 120 160 ns

t

RAS

ACTV command to DEAC or DCAB command 60 100 000 75 100 000 100 100 000 ns

t

RCD

ACTV command to READ or WRT command (see Note 12) 24 30 40 ns

t

RP

DEAC or DCAB command to ACTV , MRS, or REFR command 36 45 60 ns

†

See Parameter Measurement Information for load circuits.

‡

All references are made to the rising transition of CLK unless otherwise noted.

NOTES: 8. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced

from the rising transition of CLK that is one cycle before read latency for the READ command. Access time is measured at output
reference level 1.4 V.

9. tLZ is measured from the rising transition of CLK that is one cycle before read latency for the READ command.

10. tHZ (MAX) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.

11. See Figure 18.

12. For read or write operations with automatic deactivate, t

RCD

must be set to satisfy minimum t

RAS

.

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

17

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

ac timing requirements†‡ (continued)

’626162-12 ’626162-15 ’626162-20

MIN MAX MIN MAX MIN MAX

UNIT

t

APR

Final data out of READ-P operation to ACTV, MRS, or REFR
command

tRP + (nEP × tCK) ns

t

APW

Final data in of WRT-P operation to ACTV, MRS, or REFR command tRP + t

CK

ns

t

RWL

Final data in to DEAC or DCAB command 24 30 40 ns

t

RRD

ACTV command for one bank to ACTV command for the other bank 24 30 40 ns

t

T

Transition time, all inputs (see Note 13) 1 5 1 5 1 5 ns

t

REF

Refresh interval 32 32 32 ms

†

See Parameter Measurement Information for load circuits.

‡

All references are made to the rising transition of CLK unless otherwise noted.

NOTE 13: Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between VIH MIN and VIL MAX. This is

ensured by design but not tested.

clock timing requirements

‡§

’626162-12 ’626162-15 ’626162-20

MIN MAX MIN MAX MIN MAX

UNIT

§

Final data out to DEAC or

Read latency = 2 –1 –1 –1

n

EP

DCAB command

Read latency = 3

–2 –2 –2

cycles

DEAC or DCAB interrupt of

Read latency = 2 2 2 2

n

HZP

dat

a-out burst to DQ in the

high-impedance state

Read latency = 3

3 3 3

cycles

n

CCD

READ or WRT command to interrupting READ, WRT, DEAC, or DCAB
command

1 1 1 cycles

n

CWL

Final data in to READ or WRT command in either bank 1 1 1 cycles

n

WCD

WRT command to first data in 0 0 0 0 0 0 cycles

n

DID

ENBL or MASK command to data in 0 0 0 0 0 0 cycles

n

DOD

ENBL or MASK command to data out 2 2 2 2 2 2 cycles

n

CLE

HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command

1 1 1 1 1 1 cycles

n

RSA

MRS command to ACTV , REFR, or MRS command 2 2 2 cycles

n

CDD

DESL command to control input inhibit 0 0 0 0 0 0 cycles

‡

All references are made to the rising transition of CLK unless otherwise noted.

§

A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE
(those CLK cycles occurring during the time when CKE is asserted low).

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

The ac timing measurements are based on signal rise and fall times equal to 1 ns (tT = 1 ns) and a midpoint
reference level of 1.4 V for L VTTL. For signal rise and fall times greater than 1 ns, the reference level is changed
to VIH MIN and VIL MAX instead of the midpoint level. All specifications referring to READ commands are also
valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also
valid for WRT -P commands unless otherwise noted. All specifications referring to consecutive commands are
specified as consecutive commands for the same bank unless otherwise noted.

Tester Pin

Electronics

1.4 V

CL = 50 pF

I

OH

Output

Under

Test

50 Ω

NOTE A: Series termination resistors may be used on test

hardware for output impedance matching purposes.

(see Note A)

I

OL

Figure 8. LVTTL-Load Circuit

t

CK

CLK

t

T

t

T

tDH, tAH, tCH, t

CEH

t

T

tDH, tAH, tCH, t

CEH

t

T

tDS, tAS, tCS, t

CES

, t

CESP

t

CKL

DQ, A0–A11, CS, RAS,

CAS

, W, DQMx, CKE

DQ, A0–A11, CS, RAS,

CAS

, W, DQMx, CKE

t

CKH

tDS, tAS, tCS, t

CES

Figure 9. Input-Attribute Parameters

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

19

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

ACTV

Command

t

HZ

READ

Command

t

AC

t

OH

t

LZ

Read Latency

Figure 10. Output Parameters

n

CCD

n

CDD

t

RC

t

RCD

t

RP

t

RRD

n

RSA

READ, WRT

DESL

ACTV

ACTV, REFR

ACTV

DEAC, DCAB

ACTV

MRS

READ, READ-P, WRT, WRT-P, DEAC, DCAB
Command Disable
DEAC, DCAB
ACTV, MRS, REFR
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR
ACTV (different bank)
ACTV, MRS

t

RAS

Figure 11. Command-to-Command Parameters

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

QQQ

DEAC or

DCAB

Command

n

HZP

n

EP

READ

Command

t

HZ

NOTE A: For this example, assume read latency = 3 and burst length = 4.

Figure 12. Read Followed by Deactivate

CLK

DQ

Q

Final Data Out

t

APR

READ-P

Command

ACTV, MRS, or

REFR Command

NOTE A: For this example, assume read latency = 3 and burst length = 1.

Figure 13. Read With Auto-Deactivate

CLK

DQ

D

t

RWL

DEAC or DCAB

Command

WRT

Command

WRT

Command

D

n

CWL

NOTE A: For this example, assume burst length = 1.

Figure 14. Write Followed By Deactivate

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

21

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

D

t

APW

ACTV, MRS, or

REFR Command

WRT

Command

WRT-P

Command

D

n

CWL

Figure 15. Write With Auto-Deactivate

CLK

DQ

DQ Ignored

DQMx

WRT

Command

t

RWL

n

DOD

READ

Command

ENBL

Command

MASK

Command

Ignored

Ignored

ENBL

Command

MASK

Command

MASK

Command

n

DOD

MASK

Command

MASK

Command

DEAC or

DCAB

Command

NOTE A: For this example, assume read latency = 3 and burst length = 4.

Figure 16. DQ Masking

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

CKE

DQ

CLK

DQ DQ DQ DQ

n

CLE

t

CES

t

CEH

t

CEH

t

CES

n

CLE

Figure 17. CLK-Suspend Operation

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

CKE

CLK

CKE

CLK

t

CEH

t

CES

t

CESP

t

CESP

t

CES

t

CEH

CLK is don’t

care, but

must be

stable

before CKE

high

CLK is don’t

care, but

must be

stable

before CKE

high

Exit

power-down

mode if t

CESP

is

satisfied (new

command)

Enter

power-down

mode

Last

Data-Out

READ

(READ-P)

Operation

Last Data-In

WRT

(WRT-P)

Operation

DESL or

NOOP

command

only if t

CESP

is not

satisfied

Exit power-down

mode (new
command)

Enter

power-down

mode

Last

Data-Out

READ

(READ-P)

Operation

Last Data-In

WRT

(WRT-P)

Operation

Figure 18. Power-Down Operation

CLK

ACTV T READ T DEAC T

abcd

R0

R0 C0

PARAMETER MEASUREMENT INFORMATION

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

24

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcd

Q T R0 C0 C0 + 1 C0 + 2 C0 + 3

†

Column-address sequence depends on programmed burst type and starting column address C0 (see T able 5).

NOTE A: This example illustrates minimum t

RCD

and nEP for the ’626162-15 at 66 MHz.

Figure 19. Read Burst (read latency = 3, burst length = 4)

ACTV T WRT T DEAC T

a bcd

R0

R0 C0

efgh

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 25

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

D T R0 C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7

†

Column-address sequence depends on programmed burst type and starting column address C0 (see T able 6).

NOTE A: This example illustrates minimum t

RCD

and t

RWL

for the ’626162-15 at 66 MHz.

Figure 20. Write Burst (burst length = 8)

CKE

ACTV B WRT B DEAC B

ab

R0

R0 C0

cd

READ B

C1

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

3

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

26

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcd

D

Q

B
B

R0R0C0 C0 + 1

C1 C1 + 1

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 4).

NOTE A: This example illustrates minimum t

RCD

and nEP for the ’626162-15 at 66 MHz.

Figure 21. Write-Read Burst (read latency = 3, burst length = 2)

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

ACTV T READ T WRT-P T

abcd

R0

R0 C0

efgh ijklmnop

C1

PARAMETER MEASUREMENT INFORMATION

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 27

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefghi jklmnop

Q
D

T
T

R0R0C0 C0 +1 C0+2 C0+3 C0+ 4 C0+5 C0+ 6 C0+7

C1 C1 +1 C1+2 C1+3 C1+ 4 C1+5 C1+ 6 C1+7

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 6).

NOTE A: This example illustrates minimum t

RCD

for the ’626162-15 at 66 MHz.

Figure 22. Read-Write Burst With Automatic Deactivate (read latency = 3, burst length = 8)

PARAMETER MEASUREMENT INFORMATION

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

ACTV T READ T WRT-P T

abcd

R0

R0 C0

efgh i

C1

SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

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28

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefghi

Q
D

T
T

R0R0C0 C0 +1 C0+2 C0+3 C0+ 4 C0+5 C0+ 6 C0+7

C1

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 6).

NOTE A: This example illustrates minimum t

RCD

for the ’626162-15 at 66 MHz.

Figure 23. Read Burst – Single Write With Automatic Deactivate (read latency = 3, burst length = 8)

PARAMETER MEASUREMENT INFORMATION

R0

CLK

DQ0

DQMx

RAS
CAS

W
A10
A11

A0–A9

CS

CKE

ACTV B READ-P B

nn+1 n+2 n+3

R0

C0

n+4 n+5 n+6 n+7 n+9 n+10 n+11 n+12 n+13 n+14

n+253

n+8

n+254 n+255

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• 29

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/ T) ADDR a b c d e f g h i j k l m nopqr s..

Q B R0 C0 C0+ 1 C0+2 C0+3 C0+ 4 C0+5 C0+6 C0+ 7 255

†

Column-address sequence depends on programmed burst type and starting column address C0.

NOTE A: This example illustrates minimum t

RCD

for the ’626162-15 at 66 MHz.

Figure 24. Read Burst – Full Page (read latency = 3, burst length = 256)

R0

CLK

DQ

DQMx

RAS
CAS

W
A10
A11

A0–A9

CS

CKE

ACTV B READ- P B

abcd

R0

C0

efgh j klmnopq

C1

ACTV T

READ-P BACTV B

READ-P TACTV T

i rs

R1 R2 R3

R1 C2R2 R3

PARAMETER MEASUREMENT INFORMATION

SMJ626162

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30

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•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/ T) ADDR a b c d e f g h i j k l m nopqr s..

Q
Q
Q

B
T
B

R0
R1
R2

C0 C0 +1 C0+2 C0+3 C0 +4 C0+5 C0+6 C0+ 7

C1 C1 +1 C1+2 C1+3 C1 +4 C1+5 C1+6 C1 +7

C2 C2 +1 C2+2 . .

†

Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see T able 6).

NOTE A: This example illustrates minimum t

RCD

for the ’626162-15 at 66 MHz.

Figure 25. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8)

DQ

CLK

ACTV B

ACTV T READ T

abcd

R0

C0

ef

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

READ B

READ T

READ B READ B

R1

C1 C2 C3 C4R0 R1

PARAMETER MEASUREMENT INFORMATION

SMJ626162

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• 31

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a b c d e f ... ...

Q
Q
Q

.

B
T
B

...

R0
R1
R0

...

C0 C0 + 1

C1 C1 + 1

C2 C2 + 1

... ...

†

Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see T able 4).

Figure 26. Two-Bank Column-Interleaving Read Bursts (read latency = 3, burst length = 2)

R0

CLK

ACTV B READ B

abcd

R0

C0

efgh

C1

DEAC TWRT T

DEAC B

ACTV T

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

DQ

PARAMETER MEASUREMENT INFORMATION

R1

R1

SMJ626162

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•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q
D

B
T

R0R1C0 C0+1 C0+ 2 C0 + 3

C1 C1 + 1 C1 + 2 C1+ 3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5.)

NOTE A: This example illustrates minimum t

RCD

, nEP, and t

RWL

for the ’626162-15 at 66 MHz.

Figure 27. Read-Burst Bank B, Write-Burst Bank T (read latency = 3, burst length = 4)

DQ

CLK

ACTV B

abcd

R0

R0

ef

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

READ-P B

ACTV T WRT-P T

R1

g

R1 C0 C1

PARAMETER MEASUREMENT INFORMATION

SMJ626162

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• 33

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

D
Q

T
B

R0R1C0 C0+1 C0+ 2 C0 + 3

C1 C1 + 1 C1 + 2 C1 + 3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5).

NOTE A: This example illustrates minimum n

CWL

for the ’626162-15 at 66 MHz.

Figure 28. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency = 3, burst length = 4)

SMJ626162

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•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q
D

T
T

R0R1C0 C0+1 C0+2 C0 +3

C1 C1+1 C1+2 C1 +3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5).

NOTE A: This example illustrates minimum t

RCD

for the ’626162-15 at 66 MHz.

Figure 29. Data Mask (read latency = 3, burst length = 4)

DQ

R0

CLK

ACTV T READ T

a

b

cd

R0

C0

e

f

g

h

C1

DCABWRT T

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

PARAMETER MEASUREMENT INFORMATION
PARAMETER MEASUREMENT INFORMATION

DQ0–DQ7

CLK

ACTV B ACTV T READ T

abcd

R0

C0

ef

DQMU

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

READ B READ T READ B READ B

R1

C1 C2 C3 C4R0 R1

DQML

Hi-Z

DQ8–DQ15

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• 35

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q
Q
Q
Q

T
B
T
B

R0
R1
R0
R1

C0 C0+1

C1 C1+1

C2 C1+1

C3 C3+1

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 4).

Figure 30. Data Mask With Byte Control (read latency = 3, burst length = 2)

PARAMETER MEASUREMENT INFORMATION

R1

R0

CLK

ACTV B READ B

R0

C0

C1

DEAC TWRT TDEAC B

ACTV T

R1

DQMU

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

DQ0–DQ7

abcd

efgh

DQML

DQ8–DQ15

SMJ626162

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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q
D

T
B

R0R1C0 C0+1 C0+2 C0 +3

C1 C1+1 C1+2 C1 +3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5).

NOTE A: This example illustrates minimum t

RCD

and nEP read burst, and a minimum t

RWL

write burst for the ’626162-15 at 66 MHz.

Figure 31. Data Mask With Byte Control (read latency = 3, burst length = 4)

PARAMETER MEASUREMENT INFORMATION

DQ0–DQ7

R0

CLK

ACTV T READ T

a

b

cd

R0

C0

fh

C1

DCABWRT B

ACTV B

R1

DQML

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

DQ8–DQ15

acd fh

DQMU

b e g

R1

SMJ626162

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• 37

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q
D

T
B

R0R1C0 C0+1 C0+2 C0 +3

C1 C1+1 C1+2 C1 +3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5).

NOTE A: This example illustrates minimum t

RCD

and t

RWL

for the ’626162-15 at 66 MHz.

Figure 32. Data Mask With Cycle-by-Cycle Byte Control (read latency = 3, burst length = 4)

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

REFR DEAC T

a

R0

bcd

R0

ACTV T READ T

C0

PARAMETER MEASUREMENT INFORMATION

REFR

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•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcd

Q T R0 C0 C0+1 C0+2 C0+3

†

Column-address sequence depends on programmed burst type and starting column address C0 (see T able 5).

NOTE A: This example illustrates minimuim tRC, t

RCD

, and nEP for the ’626162-15 at 66 MHz.

Figure 33. Refresh Cycles (read latency = 3, burst length = 4)

abcd

See Note B

CLK

DCAB

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

MRS WRT-P BACTV B

R0

See Note B

See Note B

PARAMETER MEASUREMENT INFORMATION

C0R0

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• 39

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcd

D B R0 C0 C0+1 C0+2 C0 +3

†

Column-address sequence depends on programmed burst type and starting column address C0 (see T able 5).

NOTES: A. This example illustrates minimum tRP, n

RSA

, and t

RCD

for the ’626162-15 at 66 MHz.

B. See Figure 1.

Figure 34. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)

(read latency = 3, burst length = 4)

b

C0

CLK

DQ

DQMx

RAS

CAS

W

A10

A11

A0–A9

CS

CKE

ACTV T

READ T

a

c

d

R0

gh

C1

HOLD

WRT-P T

R0

PARAMETER MEASUREMENT INFORMATION

f

HOLD

e

PDE

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40

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

BURST

TYPE

BANK ROW BURST CYCLE

†

(D/Q) (B/T) ADDR a bcdefgh

Q

D

T
T

R0R1C0 C0+1 C0+2 C0 +3

C1 C1+1 C1+2 C1 +3

†

Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see T able 5).

Figure 35. CLK Suspend (HOLD) During Read Burst and Write Burst (read latency = 3, burst length = 4)

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MECHANICAL DATA

HKD (R-CDFP-F50) CERAMIC DUAL FLATPACK

50

26

0.250 (6,35)

0.370 (9,40)

0.012 (0,30)

0.020 (0,50)

Lid

4081537/B 10/95

0.026 (0,66) MIN

1

25

0.843 (21,40)

0.811 (20,60)

0.015 (0,38) MIN
(4 Places)

0.766 (19,45)

0.746 (18,95)

0.110 (2,80)

0.140 (3,55)

0.030 (0,76) MIN

0.009 (0,23)

0.004 (0,10)

0.587 (14,90)

0.555 (14,10)

0.634 (16,10)

0.665 (16,90)

0.031 (0,80)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. The leads will be gold plated.

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright  1999, Texas Instruments Incorporated