Datasheet SMJ55166-75, SMJ55166-80 Datasheet (AUSTIN)

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Page 1

a(R)

(MAX)

a(SQ)

(MAX)

c(W)

(MIN)

SMJ55166-75

80 ns 25 ns 150 nsSMJ55166-80

75 ns 23 ns 140 ns

c(P)

(MIN)

c(SC)

(MIN)

CC1

(MAX)

CC1A

(MAX)

50 ns 30 ns 160 mA 195 mA

48 ns 24 ns 165 mA 210 mA

ROW ENABLE SERIAL DATA CYCLE TIME PAGE MODE CYCLE TIME

SERIALPORT STAND-BYSERIALPORT AC-

TIVE

ACCESS TIME ACCESS TIME DRAM DRAM SERIAL

OPERATING CURRENT OPERATING CURRENT

SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Organization: – DRAM: 262144 Words × 16 Bits – SAM: 256 Words × 16 Bits

Dual-Port Accessibility – Simultaneous and Asynchronous Access From the DRAM and SAM Ports

Data-Transfer Function From the DRAM to the Serial-Data Register

(4 × 4) × 4 Block-Write Feature for Fast Area-Fill Operations; as Many as Four Memory-Address Locations Written Per Cycle From the 16-Bit On-Chip Color Register

Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design

Byte-Write Control (WEL, WEU) Provides Flexibility

Extended Data Output (EDO) for Faster System Cycle Time

Performance Ranges:

Enhanced Page-Mode Operation for Faster Access

CAS-Before-RAS (CBR) and Hidden-Refresh Modes

Long Refresh Period

Every 8 ms (Max)

Up to 45-MHz Uninterrupted Serial-Data Streams

256 Selectable Serial-Register Starting Locations

SE-Controlled Register-Status QSF

Split-Register-Transfer Read for Simplified Real-Time Register Load

Programmable Split-Register Stop Point

3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams

All Inputs/Outputs and Clocks TTL-Compatible

Compatible With JEDEC Standards

Designed to Work With the T exas Instruments Graphics Family

description

The SMJ55166 multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) module organized as 262 144 words of 16 bits each that are interfaced to a serial-data register (serial-access memory [SAM]) organized as 256 words of 16 bits each. The SMJ55166 supports three basic types of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data from any row in the DRAM to the serial register . Except during transfer operations, the SMJ55166 can be accessed simultaneously and asynchronously from the DRAM and SAM ports.

The SMJ55166 is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates are achieved by the (4 × 4) × 4 block-write feature of the device. The block-write mode allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations. As many as 64 bits of data can be written to memory during each CAS

cycle time. Also on the DRAM port, a write mask or a write-per-bit feature allows masking of any combination of the 16 inputs/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles without reloading. The SMJ55166 also offers byte control, which can be applied in write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The SMJ55166 also offers extended-data-output (EDO) mode, which is effective in both the page-mode and standard DRAM cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

98765432

J H G F E D C B A

GB PACKAGE

(BOTTOM VIEW)

TRG

SC SE V

SS SQ15 DQ15 SQ14 DQ14 V

CC SQ13

DQ13 SQ12 DQ12 V

SS SQ11 DQ11

SQ10 DQ10 V

CC SQ9 DQ9 SQ8 DQ8

DSF

NC / V

CAS QSF A0 A1 A2 A3 V

SQ0

DQ0

SQ1 DQ1

SQ2 DQ2 SQ3 DQ3

SS SQ4 DQ4 SQ5

DQ5 V

CC SQ6 DQ6 SQ7 DQ7 V

WEL

WEU

RAS

A8 A7 A6 A5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43

40 39 38 37 36 35 34 33

HKC PACKAGE

(TOP VIEW)

TERMINAL NOMENCLATURE

A0–A8 Address Inputs CAS

Column-Address Strobe DQ0 –DQ15 DRAM-Data I/O, Write-Mask Data DSF Special-Function Select NC/V

No Connect/Ground (Important: Not

connected internally to VSS) QSF Special-Function Output RAS Row-Address Strobe SC Serial Clock SE Serial Enable SQ0–SQ15 Serial-Data Output TRG Output Enable, Transfer Select V

5-V Supply (TYP) V

Ground WEL

, WEU DRAM Byte-Write-Enable Selects

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SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

GB Package Terminal Assignments — By Location

PIN PIN PIN PIN PIN PIN PIN PIN PIN

NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME

J1 DQ1 J2 SQ3 J3 DQ3 J4 DQ4 J5 DQ5 J6 DQ6 J7 SQ7 J8 WEL J9 A8 H1 DQ0 H2 SQ2 H3 DQ2 H4 SQ4 H5 SQ5 H6 SQ6 H7 DQ7 H8 WEU H9 A7 G1 SQ0 G2 SQ1 G3 V

CC2

G4 V

SS2

G6 V

CC2

G7 V

SS2

G8 RAS G9 A6

F1 TRG F2 V

SS1

F3 V

CC1

F7 V

CC1

F8 V

CC1

F9 A5

E1 SC E2 V

CC1

E8 V

SS1

E9 A4

D1 SE D2 V

SS1

D3 V

CC1

D7 V

SS1

D8 A3 D9 A2

C1 SQ15 C2 V

SS1

C3 V

CC2

C4 V

SS2

C6 V

CC2

C7 V

SS2

C8 CAS C9 A1 B1 DQ15 B2 DQ14 B3 DQ13 B4 DQ12 B5 DQ11 B6 DQ10 B7 SQ8 B8 DSF B9 A0 A1 SQ14 A2 SQ13 A3 SQ12 A4 SQ11 A5 SQ10 A6 SQ9 A7 DQ9 A8 DQ8 A9 QSF

GB Package Terminal Assignments — By Signals

PIN PIN PIN PIN PIN PIN

NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO.

A0 B9 DQ2 H3 DQ13 B3 SQ3 J2 SQ14 A1 V

CC2

A1 C9 DQ3 J3 DQ14 B2 SQ4 H4 SQ15 C1 V

SS1

A2 D9 DQ4 J4 DQ15 B1 SQ5 H5 TRG F1 V

SS1

A3 D8 DQ5 J5 DSF B8 SQ6 H6 V

CC1

E2 V

SS1

A4 E9 DQ6 J6 QSF A9 SQ7 J7 V

CC1

F3 V

SS1

A5 F9 DQ7 H7 RAS G8 SQ8 B7 V

CC1

D3 V

SS1

A6 G9 DQ8 A8 SC E1 SQ9 A6 V

CC1

F7 V

SS2

A7 H9 DQ9 A7 SE D1 SQ10 A5 V

CC1

F8 V

SS2

A8 J9 DQ10 B6 SQ0 G1 SQ11 A4 V

CC2

G3 V

SS2

CAS C8 DQ11 B5 SQ1 G2 SQ12 A3 V

CC2

C3 V

SS2

DQ0 H1 DQ12 B4 SQ2 H2 SQ13 A2 V

CC2

G6 WEL J8

DQ1 J1 WEU H8

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SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The SMJ55166 offers a split-register-transfer read (DRAM to SAM) feature for the serial register (SAM port) that enables real-time register-load implementation for truly continuous serial-data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array . For applications not requiring real-time register load (for example, loads done during CRT -retrace periods), the full-register mode of operation is retained to simplify system design.

The SAM port is designed for maximum performance, enabling data to be accessed from the SAM at serial rates up to 45 MHz. During the split-register-transfer read operations, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active.

All inputs, outputs, and clock signals on the SMJ55166 are compatible with Series 54 TTL. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility .

The SMJ55166 is offered in a 68-pin ceramic pin-grid-array package (GB suffix) and a 64-pin ceramic flatpack (HKC suffix).

The SMJ55166 and other TI multiport video RAMs are supported by a broad line of graphics processors and control devices from TI. Table 1 is a combination of Table 3 and T able 4, showing the DRAM and SAM functions with the terminal signal levels. Table 2 shows the relationship between terminal descriptions and operational modes.

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SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Split-

Status

SerialAddress Counter

Output

Buffer

Input

Buffer

Input

Buffer

Row

Buffer

Column

Buffer

DQ0–

DQ15

A0–A8

DSF

SQ0–SQ15

1 of 4 Subblocks

(see next page)

1 of 4 Subblocks

(see next page)

1 of 4 Subblocks

(see next page)

1 of 4 Subblocks

(see next page)

QSF

RAS

CAS

WEx

TRG

Special-

Function

Logic

Refresh Counter

Serial-

Output

Buffer

Timing

Generator

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SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

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functional block diagram (continued)

1 of 4 Subblocks

Refresh Counter

Row

Decoder

Split-

Status

SerialAddress Counter

Color

Address

Mask

W/B

Latch

W/B

Unlatch

MUX

Write-

Per-Bit

Control

Serial-Data

Pointer

Serial-Data

512 × 512

Memory

Array

Sense AMP

Column DEC

Special-

Function

Logic

Input

Buffer

DQi DQi+1 DQi+2 DQi+3

RAS CAS TRG

WEx

Column

Buffer

A0–A8

DSF

Row

Buffer

QSF

DRAM

Output

Buffer

DRAM

Input

Buffer

Timing

Generator

SQi SQi+1 SQi+2 SQi+3

Serial-

Output

Buffer

Page 7

SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation

Table 1. DRAM and SAM Function Table

RAS FALL

CAS

FALL

ADDRESS DQ0–DQ15

†

FUNCTION

CAS TRG WEx‡DSF DSF RAS CAS

RAS

WEL

WEU

CAS

MNE

CODE

Reserved (do not use) L L L L X X X X X — CBR refresh (no reset) and stop-point

set (CBRS)

L X L H X

Stop

Point

X X X CBRS

CBR refresh (option reset)

L X H L X X X X X CBR

CBR refresh (no reset)

L X H H X X X X X CBRN

Full-register-transfer read H L H L X

Row

Address

Tap

Point

X X RT

Split-register-transfer read H L H H X

Row

Address

Tap

Point

X X SRT

DRAM write (nonpersistent write-per-bit)

H H L L L

Row

Address

Column

Address

Write Mask

Valid Data

RWM

DRAM block write (nonpersistent write-per-bit)

H H L L H

Row

Address

Block

Address

A2–A8

Write Mask

Column

Mask

BWM

DRAM write (persistent write-per-bit)

H H L L L

Row

Address

Column

Address

Valid Data

RWM

DRAM block write (persistent write-per-bit)

H H L L H

Row

Address

Block

Address

A2–A8

Column

Mask

BWM

DRAM write (nonmasked) H H H L L

Row

Address

Column

Address

Valid Data

DRAM block write (nonmasked) H H H L H

Row

Address

Block

Address

A2–A8

Column

Mask

Load write-mask register

H H H H L

Refresh Address

X X

Write Mask

LMR

Load color register H H H H H

Refresh Address

X X

Color

Data

LCR

Legend:

Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t care

†

DQ0–DQ15 are latched on either the first falling edge of WEx

or the falling edge of CAS, whichever occurs later.

‡

Logic L is selected when either or both WEL

and WEU are low.

The column address and block address are latched on the first falling edge of CAS

CBRS cycle should be performed immediately after the power-up initialization cycle.

A0–A3, A8: don’t care; A4–A7 : stop-point code

CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.

CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.

Load write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle.

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SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

T able 2. Terminal Description Versus Operational Mode

PIN DRAM TRANSFER SAM

A0–A8 Row, column address Row address, tap point

CAS Column-address strobe, DQ output enable Tap-address strobe

DQ DRAM data I/O, write mask

DSF Block-write enable

Write-mask-register load enable Color-register load enable CBR (option reset)

Split-register-transfer enable

RAS Row-address strobe Row-address strobe

SQ output enable,

QSF output enable SC Serial clock SQ Serial-data output TRG DQ output enable Transfer enable WEL

WEU

Write enable, write-per-bit enable

QSF Serial-register status NC/V

Either make no external connection or tie to system V

†

5-V supply

†

Ground

†

For proper device operation, all VCC pins must be connected to a 5-V supply and all VSS pins must be tied to ground.

terminal definitions

address (A0–A8)

Eighteen address bits are required to decode each of the 262144 storage cell locations. Nine row-address bits are set up on pins A0–A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set up on pins A0–A8 and latched onto the chip on the falling edge of CAS

. All addresses must be stable on

or before the falling edge of RAS

and the falling edge of CAS.

During the full-register-transfer read operation, the states of A0–A8 are latched on the falling edge of RAS

select one of the 512 rows where the transfer occurs. At the falling edge of CAS

, the column-address bits A0–A8 are latched. The most significant column-address bit (A8) selects which half of the row is transferred to the SAM. The appropriate 8-bit column address (A0 –A7) selects one of 256 tap points (starting positions) for the serial-data output.

During the split-register-transfer read operation, address bit A7 is ignored at the falling edge of CAS

. An internal counter selects which half of the register is used. If the high half of the SAM is currently in use, the low half of the SAM is loaded with the low half of the DRAM half row and vice versa. Column address (A8) selects the DRAM half row. The remaining seven address bits (A0– A6) are used to select each of the 127 possible starting locations within the SAM. Locations 127 and 255 are not valid tap points.

row-address strobe (RAS

)

RAS

is similar to a chip enable so that all DRAM cycles and transfer cycles are initiated by the falling edge of

RAS

. RAS is a control input that latches the states of the row address, WEL, WEU, TRG, CAS, and DSF onto

the chip to invoke DRAM and transfer functions of the SMJ55166.

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SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

column-address strobe (CAS)

CAS

is a control input that latches the states of the column address and DSF to control DRAM and transfer

functions of the SMJ55166. CAS

also acts as output enable for the DRAM output pins DQ0 –DQ15. During

transfer operations, address bits A0–A8 are latched at the falling edge of CAS

as the start position (tap) for the

serial-data output (SQ0–SQ15).

output enable/transfer select (TRG

)

TRG

selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as

RAS

falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins DQ0–DQ15.

For transfer operation, TRG

must be brought low before RAS falls.

write-mask select, write enable (WEL

, WEU)

In DRAM operation, WEL

enables data to be written to the lower byte (DQ0–DQ7) and WEU enables data to

be written to the upper byte (DQ8–DQ15) of the DRAM. Both WEL

and WEU have to be held high together to

select the read mode. Bringing either or both WEL

and WEU low selects the write mode. WEL and WEU are

also used to select the DRAM write-per-bit mode. Holding either or both WEL

and WEU low on the falling edge

of RAS

invokes the write-per-bit operation. The SMJ55166 supports both the nonpersistent write-per-bit mode

and the persistent write-per-bit mode.

special-function select (DSF)

The DSF input is latched on the falling edge of RAS

or the first falling edge of CAS, similar to an address. DSF

determines which of the following functions is invoked on a particular cycle:

CBR refresh with reset (CBR)

CBR refresh with no reset (CBRN)

CBR refresh with no reset and stop-point set (CBRS)

Block write (BW)

Load write-mask register (LMR) loading for the persistent write-per-bit mode

Load color register (LCR) for the block-write mode

Split-register-transfer (SRT) read

DRAM-data I/O, write-mask data (DQ0–DQ15)

DRAM data is written or read through the common I/O DQ pins. The 3-state DQ-output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as either TRG

or CAS is held high.

Data does not appear at the outputs until after both CAS

and TRG have been brought low. The write mask is

latched into the device through the random DQ pins by the falling edge of RAS

and is used on all write-per-bit

cycles. In a transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle.

serial-data outputs (SQ0–SQ15)

Serial data is read from SQ. SQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of one Series 54 TTL load. The serial outputs are in the high-impedance (floating) state while the serial-enable pin, SE

, is high. The serial outputs are enabled when SE is brought low.

serial clock (SC)

Serial data is accessed out of the data register from the rising edge of SC. The SMJ55166 is designed to work with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency.

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SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

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serial enable (SE)

During serial-access operations, SE

enables/disables the SQ outputs. SE low enables the serial-data output

while SE

high disables the serial-data output. SE is also used as an enable/disable for output pin QSF.

NOTE:While SE is held high, the serial clock is not disabled. External SC pulses increment the internal serial-address counter, regardless of the state of SE

. This ungated serial-clock scheme

minimizes access time of serial output from SE

low because the serial-clock input buffer and the

serial-address counter are not disabled by SE.

special-function output (QSF)

QSF is an output pin that indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer accesses the lower (least significant) 128 bits of the SAM. When QSF is high, the pointer accesses the higher (most significant) 128 bits of the SAM. QSF changes state upon crossing a boundary between the two SAM halves.

During full-register-transfer operations, QSF can change state upon completing the cycle. This state is determined by the tap point loaded during the transfer cycle. QSF output is enabled by SE

. If SE is high, the

QSF output is in the high-impedance state.

no connect/ground (NC/V

)

NC/V

must be tied to system ground or left floating for proper device operation.

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SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional operation description

Table 3. DRAM Function Table

RAS FALL

CAS

FALL

ADDRESS DQ0–DQ15

†

FUNCTION

CAS TRG WEx‡DSF DSF RAS CAS

RAS

WEL WEU

CAS

MNE

CODE

Reserved (do not use) L L L L X X X X X — CBR refresh (no reset) and stop-point

set (CBRS)

L X L H X

Stop

Point

X X X CBRS

CBR refresh (option reset)

L X H L X X X X X CBR

CBR refresh (no reset)

L X H H X X X X X CBRN

DRAM write (nonpersistent write-per-bit)

H H L L L

Row

Address

Column

Address

Write Mask

Valid Data

RWM

DRAM block write (nonpersistent write-per-bit)

H H L L H

Row

Address

Block

Address

A2–A8

Write Mask

Column

Mask

BWM

DRAM write (persistent write-per-bit)

H H L L L

Row

Address

Column

Address

Valid Data

RWM

DRAM block write (persistent write-per-bit)

H H L L H

Row

Address

Block

Address

A2–A8

Column

Mask

BWM

DRAM write (nonmasked) H H H L L

Row

Address

Column

Address

Valid Data

DRAM block write (nonmasked) H H H L H

Row

Address

Block

Address

A2–A8

Column

Mask

Load write-mask register

H H H H L

Refresh Address

X X

Write Mask

LMR

Load color register H H H H H

Refresh Address

X X

Color

Data

LCR

Legend:

Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled X = Don’t care

†

DQ0–DQ15 are latched on either the first falling edge of WEx

or the falling edge of CAS, whichever occurs later.

‡

Logic L is selected when either or both WEL

and WEU are low.

The column address and block address are latched on the first falling edge of CAS

CBRS cycle should be performed immediately after the power-up initialization cycle.

A0–A3, A8: don’t care; A4–A7 : stop-point code

CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.

CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.

Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle.

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enhanced page mode

Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row-address setup, row-address hold, and address multiplex. The maximum RAS

low time and CAS-page-cycle time used determine the number of

columns that can be accessed. Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55166 to operate at a

higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS transitions low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CAS

. In this case, data is obtained after t

a(C)

max (access

time from CAS

low) if t

a(CA)

max (access time from column address) has been satisfied.

refresh

CAS-before-RAS (CBR) refresh

CBR refreshes are accomplished by bringing CAS low earlier than RAS. The external row address is ignored and the refresh row address is generated internally . Three types of CBR refresh cycles are available: the CBR refresh (option reset) which ends the persistent write-per-bit mode and the stop-point mode and the CBRN refresh and CBRS refresh (no reset), which do not end the persistent write-per-bit mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within the required time period, t

rf(MA)

. The output buffers remain in the high-impedance state

during the CBR refresh cycles regardless of the state of TRG

hidden refresh

A hidden refresh is accomplished by holding CAS low in the DRAM read cycle and cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.

RAS-only refresh

A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CAS and TRG are low , the output buffers remain in the high-impedance state to conserve power . Externally generated addresses must be supplied during RAS

-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row

to be refreshed.

extended data output

The SMJ55166 features extended-data output during DRAM accesses. While RAS

and TRG are low, the DRAM

output remains valid. The output remains valid even when CAS

returns high (until WEx is low), TRG is high,

or both CAS

and RAS are high (see Figure 1 and Figure 2). The extended-data-output mode functions in all read

cycles including DRAM read, page-mode read, and read-modify-write cycles (see Figure 3).

Valid Output

dis(RH)

dis(G)

RAS

CAS

DQ0 –DQ15

TRG

Figure 1. DRAM Read Cycle With RAS-Controlled Output

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SMJ55166

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MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

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extended data output (continued)

Valid Output

dis(CH)

dis(G)

RAS

CAS

DQ0 –DQ15

TRG

Figure 2. DRAM Read Cycle With CAS-Controlled Output

TRG

DQ0–DQ15

A0–A8

CAS

RAS

ColumnColumnRow

Valid OutputValid Output

a(C)

a(CA)

h(CLQ)

a(CP)

a(CA)

a(C)

Figure 3. DRAM Page-Read Cycle With Extended Output

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byte-write operation

Byte-write operations can be applied in DRAM-write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. Holding either or both WEL and WEU low selects the write mode. In normal write cycles, WEL

enables data to be written to the lower byte (DQ0–DQ7) and WEU enables data to be written to

the upper byte (DQ8–DQ15). For early-write cycles, one WEx

is brought low before CAS falls. The other WEx can be brought low before CAS falls or after CAS falls. The data is strobed in with data setup and hold times for DQ0–DQ15 referenced to CAS

(see Figure 4).

DQ0–DQ15

WEU

WEL

†

CAS

RAS

Valid Input

h(CLD)

su(DCL)

†

Either WEU or WEL can be brought low prior to CAS to initiate an early-write cycle.

Figure 4. Example of an Early-Write Cycle

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byte-write operation (continued)

For late-write or read-modify-write cycles, WEL

and WEU are both held high before CAS falls. After CAS falls,

either or both WEL

and WEU are brought low to select the corresponding byte or bytes to be written. Data is

strobed in by either or both WEL

and WEU with data setup and hold times for DQ0 – DQ15 referenced to

whichever WEx

falls earlier (see Figure 5).

DQ0–DQ15

WEU

WEL

CAS

RAS

Valid Input

h(WLD)

su(DWL)

Figure 5. Example of a Late-Write Cycle

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write-per-bit

The write-per-bit feature allows masking any combination of the 16 DQs on any write cycle. The write-per-bit operation is invoked when either WEL or WEU is held low on the falling edge of RAS. Assertion of either individual WEx

allows entry of the entire 16-bit mask on DQ0 –DQ15. Byte control of the mask input is not

allowed. If both WEL

and WEU are held high on the falling edge of RAS, the write operation is performed without any masking. The SMJ55166 offers two write-per-bit modes: nonpersistent write-per-bit and persistent write-per-bit.

nonpersistent write-per-bit

When either or both WEL and WEU are low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit mask) is input to the device through the random DQ pins and latched on the falling edge of RAS

. The write-per-bit mask selects which of the 16 random I/Os are to be written and which are not. After

RAS

has latched the on-chip write-per-bit mask, input data is driven onto the DQ pins and is latched on either

the first falling edge of WEx

or the falling edge of CAS, whichever occurs later. WEL enables the lower byte

(DQ0– DQ7) to be written through the mask and WEU

enables the upper byte (DQ8 – DQ15) to be written

through the mask. If a data low (write mask = 0) is strobed into a particular I/O pin on the falling edge of RAS

, data is not written to that I/O. If a data high (write mask = 1) is strobed into a particular I/O pin on the falling edge of RAS

, data is written to that I/O (see Figure 6).

RAS

CAS

WEL

WEU

DQ0–DQ15

su(DQR)

su(DWL)

h(RDQ)

h(WLD)

Write Mask Write Input

Figure 6. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation

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persistent write-per-bit

The persistent write-per-bit mode is initiated by performing a load-write-mask-register (LMR) cycle. In the persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary number of write cycles until another LMR cycle is performed or power is removed.

The LMR cycle is performed using DRAM write-cycle timing with DSF held high on the falling edge of RAS

and

held low on the falling edge of CAS

. A binary code is input to the write-mask register via the random I/O pins

and latched on either the first WEx

falling edge or the falling edge of CAS, whichever occurs later. Byte write control can be applied to the write mask during the LMR cycle. The persistent write-per-bit mode can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data on the falling edge of RAS

is ignored. When the device is set to the persistent write-per-bit mode, it remains in this mode and

is reset only by a CBR refresh (option reset) cycle (see Figure 7).

RAS

CAS

A0–A8

DSF

Load Write-Mask Register Persistent Write-Per-Bit

DQ0–

DQ15

Write-Mask Data

Valid Input

Mask Data = 1 : Write to I/O enabled. . . . . .

= 0 : Write to I/O disabled

CBR Refresh (option reset)

WEx

Refresh Address

Row Column

Figure 7. Example of a Persistent Write-Per-Bit Operation

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block write

The block-write feature allows up to 64 bits of data to be written simultaneously to one row of the memory array . This function is implemented as 4 columns × 4 DQs and repeated in four quadrants. In this manner, each of the four 1M-bit quadrants can have up to four consecutive columns written at a time with up to four DQs per column (see Figure 8).

DQ4

DQ14

DQ0

4 Consecutive Columns of 0–511

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ15

4th Quadrant

3rd Quadrant

2nd Quadrant

1st Quadrant

One Row of 0–511

Figure 8. Block-Write Operation

Each 1M-bit quadrant has a 4-bit column mask to mask off and prevent any or all of the four columns from being written with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to provide write-masking options. The DQ data is provided by four bits from the on-chip color register. Bits 0–3 from the 16-bit write-mask register, bits 0–3 from the 16-bit column-mask register, and bits 0–3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4–7, 8 –11, and 12–15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 9).

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block write (continued)

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

One Row of 0–511

0 1 2 3

9 10 11

12 13 14 15

Color Register

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Column MaskWrite Mask

Figure 9. Block Write With Masks

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block write (continued)

Every four columns make a block, which results in 128 blocks along one row. Block 0 comprises columns 0–3, block 1 comprises columns 4–7, block 2 comprises columns 8–11, and so forth, as shown in Figure 10.

01234567 511. . . . . . . . . . . . . . . . . . . . . . . . . . .

Columns

Block 0 Block 1 Block 127. . . . . . . . . . . . . . . . . . . . . .

One Row of 0–511

Figure 10. Block Columns Organization

During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the falling edge of CAS

to decode one of the 128 blocks. Address bits A0–A1 are ignored. Each 1M-bit quadrant has the

same block selected. A block-write cycle is entered in a manner similar to a DRAM-write cycle except DSF is held high on the first

falling edge of CAS

. As in a DRAM-write operation, WEL enables writing of the lower DRAM DQ byte while WEH enables the upper byte. The column-mask data is input via the DQs and is latched on either the first falling edge of WEx

or the falling edge of CAS, whichever occurs later. The 16-bit color-data register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section for details on use of the write-mask capability, allowing additional performance options.

Example of block write:

block-write column address = 110000000 (A0 –A8 from left to right)

bit 0 bit 15

color-data register = 1011 1011 1100 0111

write-mask register = 1110 1111 1111 1011

column-mask register = 1111 0000 01 11 1010

1st 2nd 3rd 4th

Quad Quad Quad Quad

Column-address bits A0 and A1 are ignored. Block 0 (columns 0–3) is selected for each 1M-bit quadrant. The first quadrant has DQ0–DQ2 written with bits 0–2 from the color-data register (101) to all four columns of block

0. DQ3 is not written and retains its previous data due to write-mask-register-bit 3 being a 0. The second quadrant (DQ4–DQ7) has all four columns masked off due to the column-mask bits 4–7 being 0,

so that no data is written. The third quadrant (DQ8–DQ1 1) has its four DQs written with bits 8 –11 from the color-data register (1100) to

columns 1 – 3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to column-mask-register-bit 8 being 0.

The fourth quadrant (DQ12 – DQ15) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 11 after the block-write operation shown in the previous example.

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block write (continued)

DQ12

Columns 0 1 2 3

4th Quadrant

0000

DQ13 0 0 0 0

DQ14 1 0 1 0

DQ15 1 0 1 0

Figure 11. Example of Fourth Quadrant After Block-Write Operation

load color register

The load-color-register cycle is performed using normal DRAM-write-cycle timing except that DSF is held high on the falling edges of RAS

and CAS. The color register is loaded from pins DQ0– DQ15, which are latched

on either the first falling edge of WEx

or the falling edge of CAS, whichever occurs later. If only one WEx is low , only the corresponding byte of the color register is loaded. When the color register is loaded, it retains data until power is lost or until another load-color-register cycle is performed (see Figure 12 and Figure 13).

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0–DQ15

12323

656

Load-Color-Register Cycle

Block-Write Cycle (no write mask)

Block-Write Cycle (load and use write mask)

Legend:

1. Refresh address

2. Row address

3. Block address (A2–A8) is latched on the falling edge of CAS

4. Color-register data

5. Write-mask data: DQ0–DQ15 are latched on the falling edge of RAS

6. Column-mask data: DQi–DQi + 3 (i = 0, 4, 8, 12) are latched on either the first falling edge of WEx

or the falling edge of CAS, whichever

occurs later.

= don’t care

Figure 12. Example of Block Writes

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load color register (continued)

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0–DQ15

1 23

Load-Mask-Register Cycle

Load-Color-Register Cycle

Persistent Block-Write Cycle

(use loaded write mask)

Legend:

1. Refresh address

2. Row address

3. Block address (A2–A8) is latched on the falling edge of CAS

4. Color-register data

5. Write-mask data: DQ0–DQ15 are latched on the falling edge of CAS

6. Column-mask data: DQi–DQi + 3 (i = 0, 4, 8, 12) are latched on either the first WEx

falling edge or the falling edge of CAS, whichever

occurs later.

= don’t care

Figure 13. Example of a Persistent Block Write

DRAM-to-SAM transfer operation

During the DRAM-to-SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG

low and

holding WEx

high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS , determines whether the full-register-transfer read operation or the split-register-transfer read operation is performed.

Table 4. SAM Function Table

RAS FALL

CAS

FALL

ADDRESS DQ0 –DQ15

MNE

FUNCTION

CAS TRG WEx†DSF DSF RAS CAS RAS

CAS

WEx

MNE

CODE

Full-register-transfer read H L H L X

Row Addr

Tap

Point

X X RT

Split-register-transfer read H L H H X

Row Addr

Tap

Point

X X SRT

†

Logic L is selected when either or both WEL and WEU are low.

X = don’t care

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full-register-transfer read

A full-register-transfer read operation loads data from a selected half of a row in the DRAM into the serial-access memory register (SAM). TRG

is brought low and latched at the falling edge of RAS. Nine row-address bits

(A0–A8) are also latched at the falling edge of RAS

to select one of the 512 rows available for the transfer. The

nine column-address bits (A0–A8) are latched at the falling edge of CAS

, where address bit A8 selects which half of the row is transferred. Address bits A0– A7 select each of the 256 available tap points (of the SAM register) from which the serial data is read (see Figure 14).

512 × 512 Memory Array

256-Bit Data Register

0 255 256 511

0 255

A8 = 0 A8 = 1

Figure 14. Full-Register-Transfer Read

A full-register-transfer read can be performed in three ways: early load, real-time load (or midline load), or late load. Each of these offers the flexibility of controlling the TRG

trailing edge in the full-register-transfer read cycle

(see Figure 15).

Early Load Real-Time Load Late Load

RAS

CAS

A0–A8

TRG

WEx

Row T ap

Point

Row Tap

Point

Row Tap

Point

Tap Bit

Old Data

Figure 15. Example of Full-Register-Transfer Read Operations

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split-register-transfer read

In the split-register-transfer read operation, the serial-data register is split into halves (see Figure 16). The low half contains bits 0–127, and the high half contains bits 128–255. While one half is being read out of the SAM port, the other half can be loaded from the memory array.

512 × 512 Memory Array

256-Bit Data Register

0 255 256 511

0 255

A8 = 0 A8 = 1

Figure 16. Split-Register-Transfer Read

T o invoke a split-register-transfer read cycle, DSF is brought high, TRG is brought low , and both are latched at the falling edge of RAS

. Nine row-address bits (A0– A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0–A6 and A8) are latched at the falling edge of CAS

. Column-address bit A8 selects which half of the row is to be transferred. Column-address bits A0–A6 select each of the 127 tap points in the specified half of the SAM. Column-address bit A7 is ignored, and the split-register-transfer is internally controlled to select the inactive register half (see Figure 17).

Full XFER

RAS

Split XFER Split XFER Split XFER

0511

A8 = 0

0 255

ABC

0 A7 = 0†511

A8 = 1

0 255

ABCD

0 A7 = 1†511

A8 = 1

0 255

ABCD E

0 A7 = 0

†

511

A8 = 0

0 255

DRAM

SAM

†

A7 shown as internally controlled.

Figure 17. Example of a Split-Register-Transfer Read Operation

A full-register-transfer read must precede the first split-register-transfer read to ensure proper operation. After the full-register-transfer read cycle, the first split-register-transfer read can follow immediately without any minimum SC clock requirement.

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split-register-transfer read (continued)

QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low, the serial-address pointer is accessing the lower (least significant) 128 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 128 bits of the SAM. QSF changes state upon completing a full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also changes state when a boundary between two register halves is reached (see Figure 18 and Figure 19).

RAS

CAS

DSF

TRG

QSF

Tap Point N

d(GHQSF)

Full-Register-Transfer Read

With Tap Point N

Split-RegisterTransfer Read

d(CLQSF)

Figure 18. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read

127 or 255

d(SCQSF)

RAS

CAS

DSF

TRG

QSF

Tap Point N

Split-Register-

Transfer Read

With Tap Point N

Split-RegisterTransfer Read

d(MSRL)

d(RHMS)

Figure 19. Example of Successive Split-Register-Transfer Read Operations

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serial-read operation

The serial-read operation can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant bit (bit 255), and then wrapping around to the least significant bit (bit 0), as shown in Figure 20.

255254Tap210

Figure 20. Serial-Pointer Direction for Serial Read

For split-register-transfer read operation, serial data can be read out from the active half of the SAM by clocking SC starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to the inactive half during this period, the serial pointer points next to the tap point location loaded by that split-register-transfer (see Figure 21).

127126Tap0 255254Tap128

Figure 21. Serial Pointer for Split-Register-Transfer Read – Case I

If there is no split-register-transfer read to the inactive half during this period, the serial pointer points next to bit 128 or bit 0, respectively (see Figure 22).

127126Tap0 255254Tap128

Figure 22. Serial Pointer for Split-Register-Transfer Read – Case II

split-register programmable stop point

The SMJ55166 offers programmable stop-point mode for split-register-transfer read operation. This mode can be used to improve two-dimensional drawing performance in a nonscanline data format.

In split-register-transfer read operation, the stop point is defined as a register location at which the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode, the SAM is divided into partitions whose lengths are programmed via row addresses A4 – A7 in a CBR set (CBRS) cycle. The last serial-address location of each partition is the stop point (see Figure 23).

255128

127

Partition

Length

Stop Points

Figure 23. Example of the SAM With Partitions

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split-register programmable stop point (continued)

Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is enabled by holding CAS and WEx low and DSF high on the falling edge of RAS. The falling edge of RAS also latches row addresses A4 – A7, which are used to define the SAM partition length. The other row-address inputs are don’t cares. Stop-point mode should be initiated after the initialization cycles are performed (see Table 5).

Table 5. Programming Code for Stop-Point Mode

MAXIMUM

ADDRESS AT RAS IN CBRS CYCLE

NUMBER OF

PARTITION

LENGTH

A8 A7 A6 A5 A4 A0–A3

NUMBER OF

PARTITIONS

STOP-POINT LOCATIONS

16 X L L L L X 16

15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,

191, 207, 223, 239, 255 32 X L L L H X 8 31, 63, 95, 127, 159, 191, 223, 255 64 X L L H H X 4 63, 127, 191, 255

128

(default)

X L H H H X 2 127, 255

In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines the SAM partition in which the serial output begins, and also determines at which stop point the serial output stops coming from one half of the SAM and switches to the opposite half of the SAM (see Figure 24).

255128

127

RAS

Read XFER

Split

Read XFER

Split

Tap = H1

191

Tap = L1 Tap = H2

63 H2

Read XFER

Split

Tap = L2

255 L2

63 191

SAM High HalfSAM Low Half

L1 H1

Read XFER

Full

L2 H2

Figure 24. Example of Split-Register Operation With Programmable Stop Points

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256-/512-bit compatibility of split-register programmable stop point

The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, column-address bits A Y7 and AY8 are internally swapped to assure compatibility (see Figure 25). This address-bit swap applies to the column address and is effective for all DRAM and transfer cycles. For example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don’t care and AY7 decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR (option reset) cycle is not recommended because this ends the stop-point mode and restores address bits A Y7 and AY8 to their normal functions. Consistent use of CBR cycles ensures that the SMJ55166 remains in normal mode.

512 × 512 Memory Array

256-Bit Data Register

A Y7 = 0 AY7 = 1 AY7 = 0 A Y7 = 1

0 255

A Y8 = 0 AY8 = 1

512 × 512 Memory Array

256-Bit Data Register

A Y7 = 0 AY7 = 1 AY7 = 0 A Y7 = 1

0 255

A Y8 = 0 AY8 = 1

NONSTOP POINT MODE STOP-POINT MODE

Figure 25. DRAM-to-SAM Mapping, Nonstop Point Versus Stop Point

IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately after the power-up initialization cycles are performed.

power up

T o achieve proper device operation, an initial pause of 200 µs is required after power up followed by a minimum of eight RAS

cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two

SC cycles are required to initialize the SAM port. After initialization, the internal state of the SMJ55166 is as follows:

STATE AFTER INITIALIZATION

QSF Write mode Write-mask register Color register Serial-register tap point SAM port

Defined by the transfer cycle during initialization Nonpersistent mode Undefined Undefined Defined by the transfer cycle during initialization Output mode

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any pin –1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1.1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

– 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.5 5 5.5 V

Supply voltage 0 V

High-level input voltage 2.4 6.5 V

Low-level input voltage (see Note 2) –1 0.8 V

Operating free-air temperature – 55 125 °C

NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

SAM

’55166-75 ’55166- 80

PARAMETER

TEST CONDITIONS

‡

PORT

MIN MAX MIN MAX

UNIT

High-level output voltage IOH = –1 mA 2.4 2.4 V

Low-level output voltage IOL = 2 mA 0.4 0.4 V

Input current (leakage)

VCC = 5.5 V, VI = 0 V to 5.8 V, All other pins at 0 V to V

±10 ±10 µA

Output current (leakage) (see Note 3) VCC = 5.5 V, VO = 0 V to V

±10 ±10 µA

CC1

Operating current

See Note 4 Standby 165 160 mA

CC1A

Operating current

c(SC)

= MIN Active 210 195 mA

CC2

Standby current All clocks = V

Standby 12 12 mA

CC2A

Standby current t

c(SC)

= MIN Active 70 65 mA

CC3

RAS-only refresh current See Note 4 Standby 165 160 mA

CC3A

RAS-only refresh current t

c(SC)

= MIN, (See Note 4) Active 215 195 mA

CC4

Page-mode current

c(P)

= MIN, (See Note 5) Standby 100 95 mA

CC4A

Page-mode current

c(SC)

= MIN, (See Note 5) Active 145 130 mA

CC5

CBR current See Note 4 Standby 165 160 mA

CC5A

CBR current t

c(SC)

= MIN, (See Note 4) Active 210 195 mA

CC6

Data-transfer current See Note 4 Standby 180 170 mA

CC6A

Data-transfer current t

c(SC)

= MIN Active 225 200 mA

‡

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

NOTES: 3. SE

is disabled for SQ output leakage tests.

4. Measured with one address change while RAS

= VIL and t

c(rd)

, t

c(W)

, t

c(TRD)

= MIN

5. Measured with one address change while CASx

= V

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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 6)

PARAMETER MIN TYP MAX UNIT

i(A)

Input capacitance, A0–A8 5 10 pF

i(RC)

Input capacitance, CAS and RAS 8 10 pF

i(W)

Input capacitance, WEL and WEU 7 10 pF

i(SC)

Input capacitance, SC 6 10 pF

i(SE)

Input capacitance, SE 7 10 pF

i(DSF)

Input capacitance, QSF 7 10 pF

i(TRG)

Input capacitance, TRG 7 10 pF

o(O)

Output capacitance, SQ and DQ 12 15 pF

o(QSF)

Output capacitance, QSF 10 12 pF

NOTE 6: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 7)

TEST ALT.

’55166-75 ’55166-80

PARAMETER

CONDITIONS†SYMBOL

MIN MAX MIN MAX

UNIT

a(C)

Access time from CAS t

d(RLCL)

= MAX t

CAC

20 20 ns

a(CA)

Access time from column address t

d(RLCL)

= MAX t

38 40 ns

a(CP)

Access time from CAS high t

d(RLCL)

= MAX t

CPA

43 45 ns

a(R)

Access time from RAS t

d(RLCL)

= MAX t

RAC

75 80 ns

a(G)

Access time of DQ from TRG low t

OEA

20 20 ns

a(SQ)

Access time of SQ from SC high CL = 30 pF t

SCA

23 25 ns

a(SE)

Access time of SQ from SE low CL = 30 pF t

SEA

18 20 ns

dis(CH)

Disable time, random output from CAS high (see Note 8)

CL = 50 pF t

OFF

0 20 0 20 ns

dis(RH)

Disable time, random output from RAS high (see Note 8)

CL = 50 pF 0 20 0 20 ns

dis(G)

Disable time, random output from TRG high (see Note 8)

CL = 50 pF t

OEZ

0 20 0 20 ns

dis(WL)

Disable time, random output from WE low (see Note 8)

CL = 50 pF t

WEZ

0 25 0 25 ns

dis(SE)

Disable time, serial output from SE high (see Note 8) CL = 30 pF t

SEZ

0 18 0 20 ns

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data-out reference level:

VOH / VOL = 2 V/0.8 V. Switching times for SAM-port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial-data-out reference level: VOH / VOL = 2 V/0.8 V.

8. t

dis(CH), tdis(RH)

, t

dis(G)

, t

dis(WL),

and t

dis(SE)

are specified when the output is no longer driven.

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timing requirements over recommended ranges of supply voltage and operating free-air temperature

†

ALT.

’55166-75 ’55166-80

SYMBOL

MIN MAX MIN MAX

UNIT

c(rd)

Cycle time, read t

140 150 ns

c(W)

Cycle time, write t

140 150 ns

c(rdW)

Cycle time, read-modify-write t

RMW

188 200 ns

c(P)

Cycle time, page-mode read, write t

48 50 ns

c(RDWP)

Cycle time, page-mode read-modify-write t

PRMW

88 90 ns

c(TRD)

Cycle time, transfer read t

140 150 ns

c(SC)

Cycle time, SC (see Note 9) t

SCC

24 30 ns

w(CH)

Pulse duration, CAS high t

CPN

10 10 ns

w(CL)

Pulse duration, CAS low (see Note 10) t

CAS

20 10 000 20 10 000 ns

w(RH)

Pulse duration, RAS high t

55 60 ns

w(RL)

Pulse duration, RAS low (see Note 11) t

RAS

75 10 000 80 10 000 ns

w(WL)

Pulse duration, WEx low t

13 15 ns

w(TRG)

Pulse duration, TRG low 20 20 ns

w(SCH)

Pulse duration, SC high t

9 10 ns

w(SCL)

Pulse duration, SC low t

SCP

9 10 ns

w(GH)

Pulse duration, TRG high t

20 20 ns

w(RL)P

Pulse duration, RAS low (page mode) t

RASP

75 100 000 80 100 000 ns

su(CA)

Setup time, column address before CAS low t

ASC

0 0 ns

su(SFC)

Setup time, DSF before CAS low t

FSC

0 0 ns

su(RA)

Setup time, row address before RAS low t

ASR

0 0 ns

su(WMR)

Setup time, WEx before RAS low t

WSR

0 0 ns

su(DQR)

Setup time, DQ before RAS low t

0 0 ns

su(TRG)

Setup time, TRG high before RAS low t

THS

0 0 ns

su(SFR)

Setup time, DSF low before RAS low t

FSR

0 0 ns

su(DCL)

Setup time, data valid before CAS low t

DSC

0 0 ns

su(DWL)

Setup time, data valid before WEx low t

DSW

0 0 ns

su(rd)

Setup time, read command, WEx high before CAS low t

RCS

0 0 ns

su(WCL)

Setup time, early write command, WEx low before CAS low t

WCS

0 0 ns

su(WCH)

Setup time, WEx low before CAS high, write t

CWL

18 20 ns

su(WRH)

Setup time, WEx low before RAS high, write t

RWL

20 20 ns

h(CLCA)

Hold time, column address after CAS low t

CAH

13 15 ns

h(SFC)

Hold time, DSF after CAS low t

CFH

15 15 ns

†

Timing measurements are referenced to VIL MAX and VIH MIN.

NOTES: 9. Cycle time assumes tt = 3 ns.

10. In a read-modify-write cycle, t

d(CLWL)

and t

su(WCH)

must be observed. Depending on the user’s transition times, this can require

additional CAS

low time [t

w(CL)

11. In a read-modify-write cycle, t

d(RLWL)

and t

su(WRH)

must be observed. Depending on the user’s transition times, this can require

additional RAS

low time [t

w(RL)

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)

†

ALT.

’55166-75 ’55166-80

SYMBOL

MIN MAX MIN MAX

UNIT

h(RA)

Hold time, row address after RAS low t

RAH

10 10 ns

h(TRG)

Hold time, TRG after RAS low t

THH

15 15 ns

h(RWM)

Hold time, write mask after RAS low t

RWH

15 15 ns

h(RDQ)

Hold time, DQ after RAS low (write-mask operation) t

15 15 ns

h(SFR)

Hold time, DSF after RAS low t

RFH

10 10 ns

h(RLCA)

Hold time, column address valid after RAS low (see Note 12) t

33 35 ns

h(CLD)

Hold time, data valid after CAS low t

15 15 ns

h(RLD)

Hold time, data valid after RAS low (see Note 12) t

DHR

35 35 ns

h(WLD)

Hold time, data valid after WEx low t

15 15 ns

h(CHrd)

Hold time, read, WEx high after CAS high (see Note 13) t

RCH

0 0 ns

h(RHrd)

Hold time, read, WEx high after RAS high (see Note 13) t

RRH

0 0 ns

h(CLW)

Hold time, write, WEx low after CAS low t

WCH

15 15 ns

h(RLW)

Hold time, write, WEx low after RAS low (see Note 12) t

WCR

35 35 ns

h(WLG)

Hold time, TRG high after WEx low (see Note 14) t

OEH

10 10 ns

h(SHSQ)

Hold time, SQ after SC high t

SOH

2 2 ns

h(RSF)

Hold time, DSF after RAS low t

FHR

35 35 ns

h(CLQ)

Hold time, Output after CAS low t

DHC

0 0 ns

CSH

75 80

d(RLCH)

Del

ay time,

RAS l

ow to

CAS high

(See Note 15) t

CHR

13 15

d(CHRL)

Delay time, CAS high to RAS low t

CRP

0 0 ns

d(CLRH)

Delay time, CAS low to RAS high t

RSH

20 20 ns

d(CLWL)

Delay time, CAS low to WEx low (see Notes 16 and 17) t

CWD

48 50 ns

d(RLCL)

Delay time, RAS low to CAS low (see Note 18) t

RCD

20 50 20 60 ns

d(CARH)

Delay time, column address valid to RAS high t

RAL

38 40 ns

d(CACH)

Delay time, column address valid to CAS high t

CAL

38 40 ns

d(RLWL)

Delay time, RAS low to WEx low (see Note 16) t

RWD

95 100 ns

d(CAWL)

Delay time, column address valid to WEx low (see Note 16) t

AWD

63 65 ns

d(CLRL)

Delay time, CAS low to RAS low (see Note 15) t

CSR

0 0 ns

d(RHCL)

Delay time, RAS high to CAS low (see Note 15) t

RPC

0 0 ns

d(CLGH)

Delay time, CAS low to TRG high for DRAM read cycles 20 20 ns

d(GHD)

Delay time, TRG high before data applied at DQ t

OED

15 15 ns

†

Timing measurements are referenced to VIL MAX and VIH MIN.

NOTES: 12. The minimum value is measured when t

d(RLCL)

is set to t

d(RLCL)

MIN as a reference.

13. Either t

h(RHrd)

or t

h(CHrd)

must be satisfied for a read cycle.

14. Output-enable-controlled write; the output remains in the high-impedance state for the entire cycle.

15. CBR refresh operation only

16. Read-modify-write operation only

17. TRG

must disable the output buffers prior to applying data to the DQ pins.

18. The maximum value is specified only to assure RAS

access time.

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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)

†

ALT.

’55166-75 ’55166-80

SYMBOL

MIN MAX MIN MAX

UNIT

d(RLTH)

Delay time, RAS low to TRG high (see Note 19) t

RTH

58 60 ns

d(RLSH)

Delay time, RAS low to first SC high after TRG high (see Note 20) t

RSD

75 80 ns

d(RLCA)

Delay time, RAS low to column address valid t

RAD

15 35 15 40 ns

d(GLRH)

Delay time, TRG low to RAS high t

ROH

20 20 ns

d(CLSH)

Delay time, CAS low to first SC high after TRG high (see Note 20) t

CSD

23 25 ns

d(SCTR)

Delay time, SC high to TRG high (see Notes 19 and 20) t

TSL

5 5 ns

d(THRH)

Delay time, TRG high to RAS high (see Note 19) t

TRD

–10 –10 ns

d(THRL)

Delay time, TRG high to RAS low (see Note 21) t

TRP

55 60 ns

d(THSC)

Delay time, TRG high to SC high (see Note 19) t

TSD

18 20 ns

d(RHMS)

Delay time, RAS high to last (most significant) rising edge of SC before boundary switch during split-register-transfer read cycles

20 20 ns

d(CLTH)

Delay time, CAS low to TRG high in real-time-transfer read cycles t

CTH

15 15 ns

d(CASH)

Delay time, column address to first SC in early-load-transfer read cycles t

ASD

28 30 ns

d(CAGH)

Delay time, column address to TRG high in real-time-transfer read cycles

ATH

20 20 ns

d(DCL)

Delay time, data to CAS low t

DZC

0 0 ns

d(DGL)

Delay time, data to TRG low t

DZO

0 0 ns

d(MSRL)

Delay time, last (most significant) rising edge of SC to RAS low before boundary switch during split-transfer read cycles

20 20 ns

d(SCQSF)

Delay time, last (127 or 255) rising edge of SC to QSF switching at the boundary during split-register-transfer read cycles (see Note 22)

SQD

28 30 ns

d(CLQSF)

Delay time, CAS low to QSF switching in transfer read cycles (see Note 22)

CQD

33 35 ns

d(GHQSF)

Delay time, TRG high to QSF switching in transfer read cycles (see Note 22)

TQD

28 30 ns

d(RLQSF)

Delay time, RAS low to QSF switching in transfer read cycles (see Note 22)

RQD

73 75 ns

rf(MA)

Refresh time interval, memory t

REF

8 8 ms

Transition time t

3 50 3 50 ns

†

Timing measurements are referenced to VIL MAX and VIH MIN.

NOTES: 19. Real-time-load transfer read or late-load-transfer read cycle only

20. Early-load-transfer read cycle only

21. Full-register-(read) transfer cycles only

22. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and the output reference level is VOH / VOL = 2 V/0.8 V.

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DQ0–DQ15

c(rd)

w(RL)

d(RLCH)

w(RH)

d(CLRH)

w(CL)

d(RLCL)

h(RA)

su(RA)

h(CLCA)

w(CH)

su(TRG)

w(TRG)

h(RHrd)

dis(CH)

dis(G)

a(G)

a(C)

a(R)

a(CA)

Row Column

Data OutData In

d(CARH)

d(RLCA)

d(DGL)

d(CHRL)

su(rd)

h(CHrd)

d(CLGH)

h(RLCA)

su(CA)

DSF

su(SFR)

h(SFR)

d(GLRH)

h(TRG)

d(CACH)

Figure 26. Read-Cycle Timing With CAS-Controlled Output

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DQ0–DQ15

c(rd)

w(RL)

d(RLCH)

w(RH)

d(CLRH)

w(CL)

d(RLCL)

h(RA)

su(RA)

w(CH)

su(TRG)

h(TRG)

w(TRG)

h(RHrd)

dis(RH)

dis(G)

a(G)

a(C)

a(R)

a(CA)

Row Column

Data Out

Data In

d(CARH)

d(RLCA)

d(DGL)

d(GLRH)

d(CHRL)

h(CHrd)

d(CLGH)

h(RLCA)

su(CA)

DSF

h(SFR)

su(SFR)

su(rd)

d(CACH)

h(CLCA)

Figure 27. Read-Cycle Timing With RAS-Controlled Output

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

DSF

TRG

DQ0–DQ15

c(W)

w(RL)

w(RH)

d(RLCH)

d(CLRH)

w(CL)

d(RLCL)

d(CHRL)

h(RA)

h(RLCA)

su(CA)

su(RA)

h(CLCA)

w(CH)

h(SFR)

su(SFR)

su(SFC)

h(SFC)

su(TRG)

su(WMR)

su(WCH)

su(WRH)

h(RLW)

h(CLW)

su(WCL)

h(RWM)

su(DQR)

su(DCL)

w(WL)

h(CLD)

h(RLD)

Row Column

d(CHRL)

d(CARH)

d(RLCA)

h(RDQ)

h(RSF)

h(TRG)

d(CACH)

Figure 28. Early-Write-Cycle Timing

Table 6. Early-Write-Cycle State Table

STATE

CYCLE

1 2 3

Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data

Page 37

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

c(W)

w(RL)

w(RH)

d(RLCH)

d(RLCL)

d(CLRH)

w(CL)

d(CHRL)

w(CH)

h(RA)

su(RA)

h(RLCA)

su(CA)

h(CLCA)

su(TRG)

h(RWM)

d(GHD)

su(WRH)

su(WCH)

h(RLW)

h(CLW)

su(WMR)

su(DQR)

h(RDQ)

su(DWL)

w(WL)

h(WLD)

h(RLD)

RAS

CAS

A0–A8

WEx

TRG

DQ0–DQ15

DSF

Row Column

su(SFR)

h(SFR)

h(SFC)

su(SFC)

d(CARH)

d(RLCA)

d(CHRL)

h(WLG)

h(RSF)

su(rd)

d(CACH)

Figure 29. Late-Write-Cycle Timing (Output-Enable-Controlled Write)

Table 7. Late-Write-Cycle State Table

STATE

CYCLE

1 2 3

Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data

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SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

DSF

TRG

DQ0–DQ15

c(W)

w(RL)

w(RH)

d(RLCH)

d(CLRH)

w(CL)

d(RLCL)

d(CHRL)

h(RA)

su(RA)

w(CH)

Write Mask

†

h(SFR)

su(SFR)

su(SFC)

h(SFC)

su(TRG)

su(WMR)

su(WCH)

su(WRH)

h(RLW)

h(CLW)

su(WCL)

h(RWM)

su(DCL)

w(WL)

h(CLD)

h(RLD)

d(CHRL)

h(RSF)

h(TRG)

Refresh Row

†

Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.

Figure 30. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)

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PARAMETER MEASUREMENT INFORMATION

c(W)

w(RL)

w(RH)

d(RLCH)

d(RLCL)

d(CLRH)

w(CL)

d(CHRL)

w(CH)

h(RA)

su(RA)

Write Mask

†

su(TRG)

h(RWM)

d(GHD)

su(WRH)

su(WCH)

h(RLW)

h(CLW)

su(WMR)

su(DWL)

w(WL)

h(WLD)

h(RLD)

RAS

CAS

A0–A8

WEx

TRG

DQ0–DQ15

su(SFR)

h(SFR)

h(SFC)

su(SFC)

d(CHRL)

h(WLG)

h(RSF)

DSF

Refresh Row

†

Load-write-mask-register cycle puts the device into the persistent write-per-bit mode.

Figure 31. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0–DQ15

c(rdW)

w(RL)

d(RLCL)

d(CLRH)

w(CL)

w(RH)

d(CHRL)

w(CH)

su(RA)

h(RA)

h(RLCA)

h(CLCA)

su(SFC)

h(SFC)

h(TRG)

su(rd)

su(WCH)

su(WRH)

su(TRG)

h(RLW)

h(WLG)

h(CLW)

d(CLWL)

w(WL)

su(WMR)

a(CA)

su(DQR)

a(C)

d(GHD)

h(WLD)

su(DWL)

dis(G)

a(G)

Row Column

Valid Out

d(RLCH)

d(CLGH)

d(CARH)

d(RLCA)

d(CHRL)

h(RSF)

w(TRG)

h(RWM)

d(CAWL)

h(RDQ)

a(R)

d(RLWL)

su(SFR)

d(DGL)

d(DCL)

h(SFR)

su(CA)

d(CACH)

Figure 32. Read-Write-/Read-Modify-Write-Cycle Timing

Table 8. Read-Write-/Read-Modify-Write-Cycle State Table

STATE

CYCLE

1 2 3

Write operation (nonmasked) H Don’t care Valid data Write operation with nonpersistent write-per-bit L Write mask Valid data Write operation with persistent write-per-bit L Don’t care Valid data

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PARAMETER MEASUREMENT INFORMATION

d(CLGH)

RAS

CAS

A0–A8

WEx

TRG

DSF

0– 15

w(RL)P

w(RH)

d(RLCL)

w(CL)

w(CH)

d(CLRH)

d(CHRL)

d(RLCH)

h(RA)

h(RLCA)

h(CLCA)

c(P)

d(CARH)

h(TRG)

su(WMR)

su(rd)

a(G)

a(R)

‡

a(CA)

†

a(CP)

†

dis(G)

dis(RH)

Row Column Column

Data Out

a(C)

Data In

d(DCL

)

d(DGL)

a(CA)

h(RHrd)

d(RLCA)

su(RA)

su(TRG)

su(CA)

h(SFR)

su(SFR)

Data Out

h(CLQ)

d(CACH)

dis(WL)

†

Access time is t

a(CP)

or t

a(CA)

dependent.

‡

DQ outputs can go from the high-impedance state to an invalid-data state prior to the specified access time.

NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing

specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS

and CAS to select the desired

write mode (normal, block write, etc.).

Figure 33. Enhanced-Page-Mode Read-Cycle Timing

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PARAMETER MEASUREMENT INFORMATION

w(RH)

RAS

CAS

0–

WEx

TRG

DSF

w(RL)P

d(RLCH)

d(RLCL)

w(CL)

w(CH)

c(P)

su(RA)

h(RA)

h(RLCA)

su(CA)

h(CLCA)

d(CARH)

12 2

su(TRG)

su(WMR)

h(RWM)

su(SFR)

h(SFR)

su(SFC)

su(WCH)

su(WRH)

su(DQR)

h(RDQ)

su(DCL)

†

h(CLD)

†

h(WLD)

†

h(RLD)

Row Column Column

d(CHRL)

45 5

d(RSF)

h(TRG)

See Note A

d(RLCA)

d(CLRH)

h(SFC)

su(SFC)

h(SFC)

d(CHRL)

su(DWL)

†

su(WCH)

w(WL)

d(CACH)

†

Referenced to the first falling edge of WEx

or the falling edge of CAS, whichever occurs later

NOTE A: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing

specifications. To ensure page-mode cycle time, TRG

must remain high throughout the entire page-mode operation if the late-write

feature is used. If the early-write-cycle timing is used, the state of TRG

is a don’t care after the minimum period t

h(TRG)

from the falling

edge of RAS.

Figure 34. Enhanced-Page-Mode Write-Cycle Timing

Table 9. Enhanced-Page-Mode Write-Cycle State Table

STATE

CYCLE

1 2 3 4 5

Write operation (nonmasked) L L H Don’t care Valid data Write operation with nonpersistent write-per-bit L L L Write mask Valid data Write operation with persistent write-per-bit L L L Don’t care Valid data Load-write-mask register on either the first falling edge of

WEx

or the falling edge of CAS, whichever occurs later.

‡

H L H Don’t care Write mask

‡

Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CAS is a don’t care during this cycle.

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0–DQ15

w(RL)P

d(RLCH)

c(RDWP)

d(RLCL)

w(CL)

w(CH)

d(CLRH)

w(RH)

d(CHRL)

su(RA)

su(CA)

h(RA)

h(RLCA)

12 2

su(SFR)

h(SFR)

su(SFC)

h(SFC)

su(rd)

su(WMR)

d(CLWL)

d(CAWL)

d(RLWL)

su(WCH)

d(GHD)

dis(G)

Row Column Column

Valid Out 5

Valid Out

d(CARH)

h(CLCA)

a(C)

†

d(DCL)

d(DGL)

d(RLCA)

d(CHRL)

h(RDQ)

su(DQR)

a(G)

†

a(R)

†

su(TRG)

h(TRG)

su(SFC)

a(C)

†

d(DCL)

a(CA)

†

h(WLD)

a(CP)

†

w(TRG)

su(WRH)

h(SFC)

w(WL)

d(CLGH)

su(DWL)

d(DGL)

h(RWM)

d(CLGH)

w(TRG)

su(DWL)

h(WLD)

d(GHD)

d(CACH)

su(WCH)

†

Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

NOTE A: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.

Figure 35. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing

Table 10. Enhanced-Page-Mode Read-Modify-Write-Cycle State Table

STATE

CYCLE

1 2 3 4 5

WEx

or the falling edge of CAS, whichever occurs later.

‡

H L H Don’t care Write mask

‡

Load-write-mask-register cycle sets the device to the persistent write-per-bit mode. Column address at the falling edge of CAS is a don’t care during this cycle.

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PARAMETER MEASUREMENT INFORMATION

d(CLGH)

RAS

CAS

A0–A8

WEx

TRG

DSF

–

w(RL)P

w(RH)

d(RLCL)

w(CL)

w(CH)

d(CLRH)

d(CHRL)

d(RLCH)

h(RA)

h(RLCA)

h(CLCA)

c(P)

d(CARH)

h(TRG)

su(WMR)

su(rd)

a(G)

a(R)

‡

w(WL)

su(WCL)

Row Column Column

Data Out

a(C)

Data In

d(DCL)

d(DGL)

a(CA)

†

d(RLCA)

su(RA)

su(TRG)

su(CA)

h(SFR)

su(SFR)

Data In

h(CLW)

d(CACH)

su(DCL)

dis(WL)

h(CLD)

†

Access time is t

a(CP)

or t

a(CA)

dependent.

‡

Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing

specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS

and CAS to select the desired write

mode (normal, block write, etc.).

Figure 36. Enhanced-Page-Mode Read-/Write-Cycle Timing

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

DSF

TRG

DQ0– DQ15

c(W)

w(RL)

w(RH)

d(RLCH)

d(CLRH)

w(CL)

d(RLCL)

d(CHRL)

h(RA)

w(CH)

Valid-Color Input

su(SFR)

h(SFC)

su(TRG)

h(TRG)

su(WMR)

su(WCH)

su(WRH)

h(RLW)

h(CLW)

su(WCL)

h(RWM)

su(DCL)

w(WL)

h(CLD)

h(RLD)

h(RSF)

d(CHRL)

su(SFC)

su(RA)

h(SFR)

Refresh Row

Figure 37. Load-Color-Register-Cycle Timing (Early-Write Load)

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PARAMETER MEASUREMENT INFORMATION

c(W)

w(RL)

w(RH)

d(RLCH)

d(RLCL)

d(CLRH)

w(CL)

d(CHRL)

w(CH)

h(RA)

su(RA)

Valid-Color Input

su(TRG)

d(GHD)

su(WRH)

su(WCH)

h(RLW)

h(CLW)

su(WMR)

su(DWL)

w(WL)

h(WLD)

h(RLD)

RAS

CAS

A0–A8

WEx

TRG

DQ0– DQ15

DSF

su(SFR)

h(SFR)

h(SFC)

h(WLG)

d(CHRL)

h(RSF)

su(SFC)

Refresh Row

Figure 38. Load-Color-Register-Cycle Timing (Late-Write Load)

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

DSF

TRG

DQ0–DQ15

c(W)

w(RL)

w(RH)

d(RLCH)

d(CLRH)

w(CL)

d(CHRL)

h(RA)

h(RLCA)

su(CA)

su(RA)

h(CLCA)

w(CH)

h(SFR)

su(SFR)

su(SFC)

h(SFC)

su(TRG)

su(WMR)

su(WCH)

su(WRH)

h(RLW)

h(CLW)

su(WCL)

h(RWM)

su(DQR)

su(DCL)

w(WL)

h(CLD)

h(RLD)

Row

d(CARH)

d(RLCA)

Block Address A2–A8

h(RDQ)

d(RLCL)

d(CHRL)

h(TRG)

d(CACH)

d(RSF)

Figure 39. Block-Write-Cycle Timing (Early Write)

Table 11. Block-Write-Cycle State Table

STATE

CYCLE

1 2 3

Block-write operation (nonmasked) H Don’t care Column mask Block-write operation with nonpersistent write-per-bit L Write mask Column mask Block-write operation with persistent write-per-bit L Don’t care Column mask

Write-mask data 0: I/O write disable Example:

1: I/O write enable DQ0 — column 0 (address A1 = 0, A0 = 0)

Column-mask data DQi – DQi + 3 0: column write disable DQ1 — column 1 (address A1 = 0, A0 = 1)

(i = 0, 4, 8, 12) 1: column write enable DQ2 — column 2 (address A1 = 1, A0 = 0)

DQ3 — column 3 (address A1 = 1, A0 = 1)

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PARAMETER MEASUREMENT INFORMATION

h(RSF)

c(W)

w(RL)

w(RH)

d(RLCH)

d(RLCL)

d(CLRH)

w(CL)

d(CHRL)

w(CH)

h(RA)

su(RA)

su(CA)

su(TRG)

h(RWM)

d(GHD)

su(WRH)

su(WCH)

h(RLW)

h(CLW)

su(WMR)

su(DQR)

h(RDQ)

su(DWL)

w(WL)

h(WLD)

h(RLD)

RAS

CAS

A0–A8

WEx

TRG

DQ0–DQ15

DSF

Row

su(SFR)

h(SFR)

h(SFC)

su(SFC)

d(CHRL)

d(RLCA)

d(CARH)

h(WLG)

h(RLCA)

Block Address A2–A8

h(CLCA)

d(CACH)

Figure 40. Block-Write-Cycle Timing (Late Write)

Table 12. Block-Write-Cycle State Table

STATE

CYCLE

1 2 3

Write-mask data 0: I/O write disable Example:

1: I/O write enable DQ0 — column 0 (address A1 = 0, A0 = 0)

Column-mask data DQi – DQi + 3 0: column write disable DQ1 — column 1 (address A1 = 0, A0 = 1)

(i = 0, 4, 8, 12) 1: column write enable DQ2 — column 2 (address A1 = 1, A0 = 0)

DQ3 — column 3 (address A1 = 1, A0 = 1)

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0–DQ15

w(RL)P

d(RLCH)

d(RLCL)

w(CL)

w(CH)

c(P)

d(CLRH)

d(CHRL)

w(RH

)

su(RA)

h(RA)

su(CA)

h(CLCA)

d(CARH)

su(WMR)

h(RWM)

su(SFR)

h(SFR)

h(SFC)

su(SFC)

h(SFC)

su(WCH)

w(WL)

su(WCH)

su(WRH)

su(DQR)

h(RDQ)

su(DWL)

†

su(DCL)

†

h(CLD)

†

h(WLD)

†

h(RLD)

Row

Block Address

A2–A8

23 3

Block Address

A2–A8

h(TRG)

See Note A

d(RLCA)

d(CHRL)

h(RLCA)

su(TRG)

su(SFC)

d(CACH)

†

Referenced to the first falling edge of WEx or the falling edge of CAS, whichever occurs later

NOTE A: To assure page-mode cycle time, TRG

must remain high throughout the entire page-mode operation if the late-write feature is used.

If the early write-cycle timing is used, the state of TRG

is a don’t care after the minimum period t

h(TRG)

from the falling edge of RAS.

Figure 41. Enhanced-Page-Mode Block-Write-Cycle Timing

Table 13. Enhanced-Page-Mode Block-Write-Cycle State Table

STATE

CYCLE

1 2 3

Write-mask data 0: I/O write disable Example:

1: I/O write enable DQ0 — column 0 (address A1 = 0, A0 = 0)

Column-mask data DQi – DQi + 3 0: column write disable DQ1 — column 1 (address A1 = 0, A0 = 1)

(i = 0, 4, 8, 12) 1: column write enable DQ2 — column 2 (address A1 = 1, A0 = 0)

DQ3 — column 3 (address A1 = 1, A0 = 1)

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0–A8

WEx

TRG

DSF

DQ0– DQ15

c(rd)

w(RL)

su(RA)

h(RA)

h(TRG)

su(TRG)

Row

d(CHRL)

w(RH)

d(RHCL)

Figure 42. RAS-Only Refresh-Cycle Timing

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PARAMETER MEASUREMENT INFORMATION

su(WMR)

h(RWM)

RAS

CAS

TRG

DSF

WEx

DQ0–DQ15

c(rd)

w(RH)

w(RL)

d(RHCL)

d(RLCH)

A0–A8

d(CLRL)

d(CHRL)

su(SFR)

h(SFR)

su(RA)

h(RA)

Figure 43. CBR-Refresh-Cycle Timing

Table 14. CBR-Cycle State Table

STATE

CYCLE

1 2 3

CBR refresh with option reset Don’t care L H CBR refresh with no reset Don’t care H H CBR refresh with stop-point set and no reset Stop address H L

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PARAMETER MEASUREMENT INFORMATION

su(CA)

RAS

CAS

A0–A8

TRG

DSF

DQ0– DQ15

w(RL)

w(RH)

w(RL)

w(CL)

d(RLCH)

h(CLCA)

h(RA)

h(RHrd)

Row Col

dis(CH)

a(C)

a(R)

Data Out

c(rd)

d(RLCA)

d(CHRL)

d(CARH)

d(GLRH)

a(G)

dis(G)

Memory Read Cycle Refresh Cycle Refresh Cycle

h(TRG)

su(TRG)

111

h(RA)

su(RA)

h(RA)

su(RA)

h(RA)

su(RA)

h(SFR)

su(SFR)

h(SFR)

su(SFR)

h(SFR)

su(SFR)

h(RWM)

su(WMR)

h(RWM)

su(WMR)

h(RWM)

su(WMR)

WEx

su(RA)

su(rd)

Figure 44. Hidden-Refresh-Cycle Timing

Table 15. Hidden-Refresh-Cycle State Table

STATE

CYCLE

1 2 3

CBR refresh with option reset Don’t care L H CBR refresh with no reset Don’t care H H CBR refresh with stop-point set and no option reset Stop address H L

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

DSF

TRG

WEx

A0–A8

Row

Tap Point A0–A8

Old Data Old Data New Data

c(TRD)

d(RLCL)

w(RL)

d(RLCH)

w(CL)

h(RLCA)

su(RA)

h(RA)

su(CA)

h(CLCA)

su(SFR)

su(TRG)

su(WMR)

h(RWM)

d(CLSH)

d(RLSH)

w(SCH)

a(SQ)

h(SHSQ)

c(SC)

a(SQ)

h(SHSQ)

w(RH)

h(TRG)

DQ0–DQ15

Hi-Z

QSF

Tap Point Bit A7

d(CHRL)

d(RLCA)

d(CARH)

w(GH)

d(CASH)

d(SCTR)

w(SCL)

w(SCH)

d(GHQSF)

d(RLQSF)

d(CLQSF)

h(SFR)

NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register

transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written into from the 256 corresponding columns of the selected row.

B. Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., the SQ is enabled), allowing data to be

shifted out of the registers. Also, the first bit to read from the data register after TRG

has gone high must be activated by a positive

transition of SC.

C. A0–A7: register tap point; A8: identifies the DRAM row half D. Early-load operation is defined as t

h(TRG)

min < t

h(TRG)

< t

d(RLTH)

min.

Figure 45. Full-Register-Transfer Read Timing, Early-Load Operations

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

DSF

TRG

WEx

A0–A8

Row

Old Data Old Data Old Data New Data

c(TRD)

d(RLCL)

w(RL)

d(RLCH)

w(CL)

h(RLCA)

su(RA)

h(RA)

su(CA)

h(CLCA)

su(SFR)

su(TRG)

su(WMR)

h(RWM)

d(THRH)

d(THRL)

d(THSC)

w(SCH)

a(SQ)

h(SHSQ)

c(SC)

a(SQ)

h(SHSQ)

w(RH)

d(RLTH)

w(SCL)

d(SCTR)

d(CHRL)

QSF

Tap Point Bit A7

d(GHQSF)

d(RLQSF)

d(CLQSF)

DQ0–DQ15

Hi-Z

w(GH)

h(SFR)

d(CLTH)

d(CAGH)

Tap Point A0–A8

d(RLCA)

NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register

transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register are written into from the 256 corresponding columns of the selected row.

B. Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., the SQ is enabled), allowing data to be

shifted out of the registers. Also, the first bit to read from the data register after TRG

has gone high must be activated by a positive

transition of SC. C. A0–A7: register tap point; A8: identifies the DRAM row half D. Late load operation is defined as t

d(THRH)

< 0 ns.

Figure 46. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation

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PARAMETER MEASUREMENT INFORMATION

c(TRD)

w(RL)

d(RLCL)

d(RLCH)

w(CL)

h(RA)

su(CA)

h(CLCA)

su(TRG)

h(TRG)

h(SFR)

su(WMR)

h(RWM)

su(SFR)

MSB Old New MSB

Row

Tap Point A0–A8

d(RHMS)

w(SCH)

a(SQ)

h(SHSQ)

Bit 127 or 255

Bit 255 or 127

Tap Point N

Bit 126 or Bit 254

H L

RAS

CAS

A0–A8

WEx

TRG

DSF

QSF

Bit 127 or Bit 255

Tap Point N

c(SC)

w(CH)

d(CHRL)

Tap Point M

d(SCQSF)

d(MSRL)

c(SC)

w(SCL)

d(SCQSF)

a(SQ)

Tap Point M

Bit 127 or Bit 255

d(RLCA)

w(SCL)

su(RA)

w(RH)

0– 15

Hi-Z

See Note A

NOTE A: A0–A6: tap point of the given half; A7: don’t care; A8: identifies the DRAM row half

Figure 47. Split-Register-Transfer Read Timing

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PARAMETER MEASUREMENT INFORMATION

w(SCH)

w(SCL)

w(SCH)

w(SCL)

w(SCH)

h(TRG)

su(TRG)

a(SQ)

h(SHSQ)

a(SE)

c(SC)

RAS

TRG

Valid Out Valid Out Valid Out

a(SQ)

h(SHSQ)

a(SQ)

h(SHSQ)

NOTES: A. While reading data through the serial-data register, TRG is a don’t care, but TRG must be held high when RAS goes low. This

is to avoid the initiation of a register-data-transfer operation. B. The serial-data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put

into the read mode by performing a transfer-read cycle.

Figure 48. Serial-Read-Cycle Timing (SE = VIL)

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PARAMETER MEASUREMENT INFORMATION

w(SCH)

w(SCL)

w(SCH)

w(SCL)

w(SCH)

h(TRG)

su(TRG)

a(SQ)

h(SHSQ)

a(SQ)

c(SC)

RAS

TRG

dis(SE)

a(SQ)

a(SE)

Valid Out Valid Out Valid Out Valid Out

NOTES: A. While reading data through the serial-data register, TRG

is a don’t care, but TRG must be held high when RAS goes low. This

is to avoid the initiation of a register-data-transfer operation.

B. The serial-data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be

put into the read mode by performing a transfer-read cycle.

Figure 49. Serial-Read Timing (SE-Controlled Read)

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PARAMETER MEASUREMENT INFORMATION

RAS

CAS

ADDR

TRG

DSF

CASE I

QSF

CASE II

ASE III

Tap1 (low)

Bit 127

Tap1 (high)

Bit 255

Tap2 (low)

Bit 127

Tap1 (low)

Row Tap1

(high)

Row Tap2

(low)

Row Tap2

(high)

Row

Tap1 (low)

Tap2 (low)

Bit 127

Bit 255

Bit 127

Tap1 (low)

Tap2 (low)

Bit 127

Bit 255

Bit 127

Tap1 (high)

Full-Register-Transfer Read

Split Register to the High Half of the Data Register

Split Register to the Low Half of the Data Register

Split Register to the High Half of the Data Register

NOTES: A. To achieve proper split-register operation, a full-register-transfer read should be performed before the first split-register-transfer

cycle. This is necessary to initialize the data register and the starting tap location. First serial access can begin after the

full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after the first

split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read cycle

and the first split-register cycle. B. A split-register transfer into the inactive half is not allowed until t

d(MSRL)

is met. t

d(MSRL)

is the minimum delay time between the

rising edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS

of the split-register-transfer cycle into the

inactive half. After the t

d(MSRL)

is met, the split-register transfer into the inactive half must also satisfy the minimum t

d(RHMS)

requirement. t

d(RHMS)

is the minimum delay time between the rising edge of RAS

of the split-register-transfer cycle into the inactive

half and the rising edge of the serial clock of the last bit (bit 127 or 255).

Figure 50. Split-Register Operating Sequence

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

GB (S-CPGA-P68) CERAMIC PIN GRID ARRAY PACKAGE

4040114-14/A 2/95

4 Places

0.800 (20,32) TYP

0.050 (1,27) DIA

0.045 (1,14)

0.018 (0,46) DIA TYP

0.055 (1,39)

E D C

123456789

0.100 (2,54)

0.166 (4,22)

0.194 (4,93)

0.072 (1,83)

0.088 (2,23)

0.950 (24,13)

0.970 (24,63)

0.524 (13,31)

0.536 (13,61)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Index mark may appear on top or bottom depending on package vendor. D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within

0.015 (0,38) radius relative to the center of the ceramic.

E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.

F. The pins can be gold plated or solder dipped.

G. Falls within MIL-STD-1835 CMGA1-PN and CMGA13-PN and JEDEC MO-067AA and MO-066AA, respectively

Page 60

SMJ55166 262144 BY 16-BIT MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

HKC (R-CDFP-F64) CERAMIC DUAL FLATPACK WITH TIE BAR

4073160/B 10/94

0.445 (11,30)

0.420 (10,67)

0.185 (4,70)

0.145 (3,68)

0.0098 (0,250)

0.0060 (0,150)

0.070 (1,78)

0.055 (1,40)

0.150 (3,81)

0.100 (2,54)

0.026 (0,66) MIN

0.320 (8,13)

0.295 (7,49)

0.0079 (0,200)

0.0043 (0,110)

0.040 (1,02)

0.030 (0,76)

0.765 (19,43)

0.730 (18,54)

1.020 (25,91)

0.980 (24,89)

1.580 (40,13)

1.620 (41,14)

0.0196 (0,500)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. All leads not shown for clarity purposes.

device symbolization

SMJ55166 HKC

LLLXXXARF

-SS Speed (-70, -80)

Die Revision Code

Assembly Site Code

Wafer Fab Code

Date Code

Lot Traceability Code

Package Code

Temperature Range

Page 61

SMJ55166

262144 BY 16-BIT

MULTIPORT VIDEO RAM

SGMS057C – APRIL 1995 – REVISED JUNE 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Page 62

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SMJ55166-75, SMJ55166-80 Datasheet (AUSTIN)

Specifications and Main Features

Frequently Asked Questions

User Manual