Datasheet SMJ27C512-20JM, SMJ27C512-25JM Datasheet (AUSTIN)

Austin Semiconductor, Inc.

512K UVEPROM

UV Erasable Programmable
Read-Only Memory

UVEPROM

SMJ27C512

PIN ASSIGNMENT

(Top Vie w)

AVAILABLE AS MILITARY
SPECIFICATIONS

• SMD 5962-87648

• MIL-STD-883

FEATURES

• Organized 65,536 x 8

• High-reliability MIL-PRF-38535 processing

• Single +5V ±10% power supply

• Pin-compatible with existing 512K read-only memories (ROMs)
and electrically programmable ROMs (EPROMs)

• All inputs/outputs fully TTL compatible

• Power-saving CMOS technology

• V ery high-speed SNAP! Pulse Programming

• 3-state output buffers

• 400mV minimum DC noise immunity with standard TTL loads

• Latchup immunity of 250mA on all input and output lines

• Low power dissipation (CMOS input levels)

PActive - 193mW (MAX)
PStandby - 1.7mW (MAX)

OPTIONS MARKING

• Timing

150ns access -15
200ns access -20
250ns access -25

• Package(s)

Ceramic DIP (600mils) J No. 110

• Operating Temperature Ranges

Military (-55oC to +125oC) M

For more products and information

please visit our web site at

www.austinsemiconductor.com

SMJ27512

Rev. 1.0 9/01

28-Pin DIP (J) 600-Mils

1

A15
A12

DQ0
DQ1
DQ2

GND

2
3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11
12
13
14

Vcc

28

A14

27

A13

26

A8

25

A9

24

A11

23

G\/V

22

PP

A10

21

E\

20

DQ7

19
18

DQ6

17

DQ5

16

DQ4

15

DQ3

Pin Name Function

A0 - A15 Address Inputs

DA0-DQ7 Inputs (programming)/Outputs

E\ Chip Enable/Power Down

GND Ground

G\ /V

V

Output Enable/13V Programming

PP

5V Power Supply

CC

GENERAL DESCRIPTION

The SMJ27C512 is a set of 65536 by 8-bit (524,288-bit),

ultraviolet (UV) light erasable, electrically programmable
read-only memories. These devices are fabricated using
power-saving CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All inputs
(including program data inputs can be driven by Series 54 TTL
circuits without the use of external pullup resistors. Each
output can drive one Series 54 TTL circuit without external
resistors. The data outputs are 3-state for connecting
multiple devices to a common bus. The SMJ27C512 is
pin-compatible with existing 28-pin 512K ROMs and
EPROMs.
Because this EPROM operates from a single 5V supply (in
the read mode), it is ideal for use in microprocessor-based
systems. One other supply (13V) is needed for programming.
All programming signals are TTL level. This device is
programmable by the SNAP! Pulse programming algorithm.

The SNAP! Pulse programming algorithm uses a VPP of 13V
and a VCC of 6.5V for a nominal programming time of seven

seconds. For programming outside the system, existing
EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

9

FUNCTIONAL BLOCK DIAGRAM*

EPROM 65,536 x 8

10

A0
A1

8

A2

7

A3

6

A4

5

A5 DQ0

4

A6 DQ1

3

A7 DQ2

25

A8 DQ3

24

A9 DQ4

E\

21
23

2

26
27
1

20

A10 DQ5
A11 DQ6
A12 DQ7
A13
A14
A15

22

G\ /V

PP

0

A

15
[PWR DWN]

&

EN

0

65,535

A
A
A
A
A
A
A
A

UVEPROM

SMJ27C512

11
12
13
15

16
17
18
19

* This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

OPERATION

The seven modes of operation for the SMJ27C512 are listed in Table 1. The read mode requires a single 5V supply. All
inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and 12V on A9 for signature mode.

TABLE 1. OPERATION MODES

FUNCTION

(PINS)

READ

E\ (20)

G\ /VPP (22) V

V

(28) V

CC

V

IL
IL

CC

OUTPUT

DISABLE

V

IL

V

IH

V

CC

STANDBY PROGRAMMING VERIFY

V

IH

X

V

CC

A9 (24) X X X X X X
A0 (10) X X X X X X

DQ0-DQ7

(11-13, 15-19)

* X can be VIL or V

SMJ27512

Rev. 1.0 9/01

Data Out High-Z High-Z

IH

MODE*

PROGRAM

INHIBIT

V

IL

V

PP

V

CC

V

IL

V

IL

V

CC

V

IH

V

PP

V

CC

Data In Data Out High-Z

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

SIGNATURE MODE

V

IL

V

IL

V

CC

V

ID

V

IL

V

ID

V

IH

CODE

MFG DEVICE

97h 85h

Austin Semiconductor, Inc.

UVEPROM

SMJ27C512

READ/OUTPUT DISABLE

When the outputs of two or more SMJ27C512 are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from
competing outputs of the other devices. T o read the output of
the selected SMJ27C512, a low-level signal is applied to the

E\ and G\ /VPP. All other devices in the circuit should have
their outputs disabled by applying a high-level signal to one of
these pins. Output data is accessed at pins DQ0 through DQ7.

LA TCHUP IMMUNITY

Latchup immunity on the SMJ27C512 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input/output
layout approach controls latchup without compromising
performance or packing density.

POWER DOWN

Active ICC supply current can be reduced from 35mA to
500µA(TTL-level inputs) or 300µA (CMOS-level inputs) by
applying a high TTL/CMOS signal to the E\ pin. In this mode
all outputs are in the high-impedance state.

SNAP! PULSE PROGRAMMING

The SMJ27C512 is programmed using the SNAP! Pulse
programming algorithm as illustrated by the flowchart in
Figure 1. This algorithm programs in a nominal time of seven
seconds. Actual programming time varies as a function of the
programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed. The SNAP!
Pulse programming algorithm uses an initial pulse of 100µs
followed by a byte verification to determine when the addressed
byte has been successfully programmed. Up to ten 100µs
pulses per byte are provided before a failure is recognized.

The programming mode is achieved when G\ /V
VCC= 6.5V, and E\ = VIL. More than one device can be

programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is complete, all bits are verified

with VCC = 5V, G\ /VPP = VIL, and E\ = VIL.

PP

= 13V,

PROGRAM INHIBIT

Programming can be inhibited by maintaining high level
input on E\.

ERASURE

Before programming, the SMJ27512 is erased by exposing
the chip through the transparent lid to a high-intensity ultra­violet (UV) light (wavelength 2537 Å). EPROM erasure
before programming is necessary to assure that all bits are in
the logic-high state. Logic lows are programmed into the
desired locations. A programmed logic low can be erased
only by ultraviolet light. The recommended minimum

exposure dose (UV intensity x exposure time) is 15 W.s/cm2.
A typical 12mW/cm2, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using
the SMJ27C512, the window should be covered with an opaque
label.

PROGRAM VERIFY

Programmed bits can be verified with G\ /VPP and E\ = VIL.

SIGNA TURE MODE

The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 (terminal 24) is forced to 12V ±0.5V. Two
identifier bytes are accessed by A0 (terminal 10); i.e.,

A0 = VIL accesses the manufacturer code, which is output on
DQ0-DQ7; A0 = VIH accesses the device code, which is also
output on DQ0-DQ7. All other addresses must be held at VIL.

Each byte possesses odd parity on bit DQ7. The
manufacturer code for these devices is 97h and the device
code is 85h.

SMJ27512

Rev. 1.0 9/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

UVEPROM

SMJ27C512

Austin Semiconductor, Inc.

FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART

START

Address = First Location

Increment

Address

VCC = 6.5V ± 0.25V, G\ /VPP = 13V ± 0.25V

Program One Pulse = tW = 100µs

Last

Address?

Yes

Address = First Location

X = 0

Verify

Word

Pass

Fail

X = X+1

Program

Mode

Increment Address

Program One Pulse = tW = 100µs

No

X = 10?

Interactive

Mode

SMJ27512

Rev. 1.0 9/01

No

VCC = 5V ± 0.5V, G\ /VPP = V

Last

Address?

Yes

Compare
All Bytes

to Original

Data

Pass

Device Passed

IL

Fail

Yes

Device Failed

Final

Verification

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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Austin Semiconductor, Inc.

UVEPROM

SMJ27C512

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage Range, VCC**...........................-0.6V to +7.0V

Supply Voltage Range, Vpp**.........................-0.6V to +14.0V

Input Voltage Range, All inputs except A9**....-0.6V to 6.5V

A9....-0.6V to +13.5V

Output Voltage Range**...............................-0.6V to VCC +1V

Operating Cage Temperature Range, TC.........-55°C to 125°C

Storage Temperature Range, T

.....................-65°C to 150°C

stg

*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
** All voltage values are with respect to GND.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Read Mode

V

CC

G\ /V

V

Supply Voltage
Supply Voltage

PP

Voltage level on A9 for signature mode

ID

1

SNAP! Pulse programming algorithm

2

SNAP! Pulse programming algorithm

TTL 2

High-level DC input voltageV

IH

V
T

NOTES:

1. VCC must be applied before or at the same time as G\ /VPP and removed after or at the same time as G\ /VPP. The deivce must not be inserted into or removed
from the board when G\ /VPP or VCC is applied.

2. G\ /VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case is ICC + IPP.

Low-level DC input voltage

IL

Operating case temperature

C

CMOS
TTL -0.5 0.8 V

CMOS -0.5 0.2 V

4.5 5 5.5 V

6.25 6.5 6.75 V

12.75 13 13.25 V

11.5 12.5 V
V

+1

CC

V

-0.2 VCC+1

CC

-55 125 °C

V
V

ELECTRICAL CHARACTERISTICS O VER RECOMMENDED RANGES OF
OPERA TING CONDITIONS

PARAMETER

V

V

I

I

NOTES:

1. Typical values are at TC=25°C and nominal voltages.

2. This parameter has been characterized at 25°C and is not production tested.

SMJ27512

Rev. 1.0 9/01

High-level output voltage

OH

Low-level output voltage

OL

Input current (leakage)

I

I

Output current (leakage)

I

O

I

PP

CC1VCC

CC2

supply current (during program pulse)

G\ /V

PP

supply current (standby)

supply current (active)

V

CC

2

TTL-Input Level
CMOS-Input Level

TEST CONDITIONS MIN

IOH = -400µA
IOL = 2.1mA
VI = 0V to 5.5V
VO = 0V to V
G\ /VPP = 13V

= 5.5V, E\=V

V

CC

V

= 5.5V, E\=V

CC

E\=VIL, VCC=5.5V
t

= minimum cycle time,

cycle

outputs open

CC

IH
CC

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

2.4

1

TYP

35 70

35 50

MAX

0.4
10
10

500
325

UVEPROM

SMJ27C512

Austin Semiconductor, Inc.

CAPACITANCE O VER RECOMMENDED RANGES OF SUPPLY VOLT AGE AND
OPERATING CASE TEMPERATURE, f = 1MHz*

PARAMETER

C

C

C

G/VPP

* Capacitance measurements are made on sample basis only.
** All typical values are at T

Input capacitance

I

Output capacitance

O

G\ /VPP input capacitance G\ /V

= 25°C and nominal voltages.

C

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPL Y
VOLTAGE AND OPERATING CASE TEMPERA TURE

PARAMETER

Access time from address 150 200 250 ns

t

a(A)

t

Access time from E\ 150 200 250 ns

a(E)

Output enable time from G\ /V

t

en(G)

Output disable time from G\ /VPP or E\,

t

dis

whichever occurs first
Output data valid time after change of

t

v(A)

address, E\, or G\, whichever occurs first

NOTES:

1. Timing measurements are made at 2V for logic high and 0.8V for logic low. (see Figure 2)

2. Common test conditions apply for t

3. V alue calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested.

3

except during programming.

dis

TEST CONDITIONS TYP** UNIT

6pF
10 pF
20

1,2

-15 -25

MIN MAX MIN MAX MIN MAX

0 50 0 60 0 60 ns

000 ns

PP

V

I

V

O

CONDITIONS

3

= 0V

= 0V

= 0V

PP

TEST

See Figure 2

pF

-20

70 75 100 ns

UNIT

RECOMMENDED TIMING REQUIREMENTS FOR PROGRAMMING: VCC = 6.5V and
G\ /VPP = 13V (SNAP! Pulse), TC = 25°C (see Figure 2)

MIN NOM MAX UNIT

t

dis(E)

t

h(A)

t

h(D)

t

h(VPP)

t

w(IPGM)

t

rec(PG)

t

su(A)

t

su(D)

t

su(Vpp)

t

su(Vcc)

t

v(ELD)

t

r(PG)

SMJ27512

Rev. 1.0 9/01

Output disable time from E\
Hold Time, address

Hold time, address
Hold time, G\ /V

PP

Pulse duration, initial program
Recovery time, G\ /V

PP

Setup Time, Address
Setup Time, Data
Setup Time, G\ /V
Setup Time, V

PP

CC

Data valid from E\ low
G\ /V

rise time

PP

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6

0 130 ns
0µs

2µs
2µs

95 100 105 µs

2µs
2µs
2µs
2µs
2µs

1µs

50 ns

Austin Semiconductor, Inc.

PARAMETER MEASUREMENT INFORMATION

2.08V

RL = 800Ω

Output Under Test

UVEPROM

SMJ27C512

CL = 100 pF

NOTES:

1. CL includes probe and fixture capacitance.

1

FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORM

AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low . Timing measurements are made
at 2V for logic high and 0.8V for logic low for both inputs and outputs.

FIGURE 3. READ-CYCLE TIMING

SMJ27512

Rev. 1.0 9/01

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7

UVEPROM

SMJ27C512

Austin Semiconductor, Inc.

FIGURE 4. PROGRAM-CYCLE TIMING (SNAP! PULSE PROGRAMMING)

NOTES:

1. G\ /V

PP

SMJ27512

Rev. 1.0 9/01

= 13V and VCC = 6.5V for SNAP! Pulse programming.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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Austin Semiconductor, Inc.

MAX

MECHANICAL DEFINITION*

ASI Case #110 (Package Designator J)

SMD 5962-87648, Case Outline X

UVEPROM

SMJ27C512

Pin 1

D

E

S1

eA

SMD SPECIFICATIONS

SYMBOL

A --- 0.232
b 0.014 0.026

b2 0.045 0.065

c 0.008 0.018
D --- 1.490
E 0.500 0.610

eA

e

L 0.125 0.200
Q 0.015 0.060

S1 0.005 --­S2 0.005 ---

MIN

0.600 BSC

0.100 BSC

b2

c

S2

A

Q

L

e

b

*All measurements are in inches.

SMJ27512

Rev. 1.0 9/01

NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

ORDERING INFORMATION

UVEPROM

SMJ27C512

EXAMPLE:

Device Number

SMJ27C512 -15 J *
SMJ27C512 -20 J *
SMJ27C512 -25 J *

SMJ27C512-25JM

Speed nsPackage

Type

Operating

Temp.

*A VAILABLE PROCESSES

M = Extended T emperature Range -55oC to +125oC

SMJ27512

Rev. 1.0 9/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

10

Austin Semiconductor, Inc.

ASI TO DSCC PART NUMBER

CROSS REFERENCE*

ASI Pac kage Designator J

TI Part #** SMD Part #

SMJ27C512-15JM 5962-8764801XA
SMJ27C512-20JM 5962-8764802XA
SMJ27C512-25JM 5962-8764803XA

UVEPROM

SMJ27C512

* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.

SMJ27512

Rev. 1.0 9/01

11

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.