The SMJ27C256 series is a set of 262,144 bit, ultravioletlight erasable, electrically programmable read-only
memories. These devices are fabricated using power-saving
CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data
inputs) can be driven by Series 54 TTL circuits without the
use of external pullup resistors. Each output can drive one
Series 54 TTL circuit without external resistors. The data
outputs are 3-state for connecting multiple devices to a
common bus. The SMJ27C256 is pin-compatible with
28-pin 256K ROMs and EPROMs. It is offered in a 600mil
dual-in-line ceramic pagackage (J suffix) rated for operation
from -55°C to 125°C.
Because this EPROM operates from a single 5V supply (in
the read mode), it is ideal for use in microprocessor-based
systems. One other supply (13V) is needed for programming.
All programming signals are TTL level. This device is
programmable by the SNAP! Pulse programming algorithm.
The SNAP! Pulse programming algorithm uses a VPP of 13V
and a VCC of 6.5V for a nominal programming time of four
seconds. For programming outside the system, existing
EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
SMJ27C256
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Page 2
Austin Semiconductor, Inc.
9
FUNCTIONAL BLOCK DIAGRAM*
EPROM 32,768 x 8
10
A0
A1
8
A2
A3
6
A4
A5DQ0
4
A6DQ1
A7DQ2
25
A8DQ3
24
A9DQ4
E\
G\
21
23
2
26
27
20
22
[PWR DWN]
&
A10DQ5
A11DQ6
A12DQ7
A13
A14
A
EN
0
32,767
A
A
A
A
A
A
A
A
11
12
13
15
16
17
18
19
UVEPROM
SMJ27C256
* This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12.
OPERATION
The seven modes of operation for the SMJ27C256 are listed in Table 1. The read mode requires a single 5V supply. All
inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and (12V) on A9 for signature mode.
T ABLE 1. OPERA TION MODES
2
V
V
V
PP
V
CC
MODE*
PROGRAM
INHIBIT
IL
IH
V
IH
V
IL
V
PP
V
CC
V
IH
X
V
PP
V
CC
SIGNATURE MODE
V
V
V
ID
V
IL
CODE
MFGDEVICE
97
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
V
IL
V
IL
CC
CC
V
V
04
FUNCTION
(PINS)
E\ (20)
G\ (22)
V
(1)V
PP
V
(28)V
CC
READ
V
V
IL
IL
CC
CC
OUTPUT
DISABLE
V
IL
V
IH
V
CC
V
CC
STANDBY PROGRAMMINGVERIFY
V
IH
X
V
CC
V
CC
A9 (24)XXXXXX
A0 (10)XXXXXX
DQ0-DQ7
(11-13, 15-19)
* X can be VIL or VIH.
SMJ27C256
Rev. 1.0 9/01
Data OutHigh-ZHigh-ZData InData OutHigh-Z
ID
IH
Page 3
Austin Semiconductor, Inc.
UVEPROM
SMJ27C256
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C256s are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from the
competing outputs of the other devices. T o read the output of
the selected SMJ27C256, a low-level signal is applied to E\
and G\. All other devices in the circuit should have their
outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
LA TCHUP IMMUNITY
Latchup immunity on the SMJ27C256 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to industry
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance
or packing density.
POWER DOWN
Active ICC supply current can be reduced from 25mA
(SMJ27C256-15 through SMJ27C256-25) to 500µA (TTLlevel inputs) or 300µA (CMOS-level inputs) by applying a high
TTL/CMOS signal to the E\ pin. In this mode all outputs are
in the high-impedance state.
ERASURE
Before programming, the SMJ27C256 is erased by exposing
the chip through the transparent lid to a high-intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before
programming is necessary to ensure that all bits are in the
logic-high state. Logic-lows are programmed into the desired
locations. A programmed logic-low can be erased only by
ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15W•s/cm2. A typical
12mW/cm2, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using the
SMJ27C256, the window should be covered with an opaque
label.
SNAP! PULSE PROGRAMMING
The SMJ27C256 EPROM is programmed by using the SNAP!
Pulse programming algorithm as illustrated by the flowchart
in Figure 1. This algorithm programs the device in a nominal
time of 4 seconds. Actual programming time varies as a
function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses
of 100 microseconds (µs) followed by a byte-verification step
to determine when the addressed byte has been successfully
programmed. Up to ten 100µs pulses per byte are provided
before a failure is recognized.
The programming mode is achieved when V
VCC= 6.5V, G\ = VIH, and E\ = VIL. More than one device can
be programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is completed, all bits are verified
with VCC = VPP = 5V.
PP
= 13V,
PROGRAM INHIBIT
Programming can be inhibited by maintaining a high-level
input on E\.
PROGRAM VERIFY
Programmed bits can be verified with VPP = 13V when
G\ = VIL, and E\ = VIH.
SIGNA TURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 is forced to 12V ±0.5V. Two identifier
bytes are accessed by A0 (terminal 10); i.e., A0=VIL accesses
the manufacturer code, which is output on DQ0-DQ7; A0=V
accesses the device code, which is also output on DQ0-DQ7.
All other addresses must be held at VIL. Each byte contains
odd parity on bit DQ7. The manufacturer code for these
devices is 97h and the device code is 04h.
IH
SMJ27C256
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Page 4
UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART
START
Address = First Location
Increment
Address
VCC = 6.5V, VPP = 13V
Program One Pulse = tW = 100µs
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t
Verify
Byte
Pass
Fail
X = X+1
Increment Address
= 100µs
W(E)PR
No
X = 10?
Program
Mode
Interactive
Mode
SMJ27C256
Rev. 1.0 9/01
No
VCC = VPP = 5V ± 10%
Last
Address?
Yes
Compare
All Bytes
to Original
Data
Pass
Device Passed
Fail
4
Yes
Device Failed
Final
Verification
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Page 5
Austin Semiconductor, Inc.
UVEPROM
SMJ27C256
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range, VCC**...........................-0.6V to +7.0V
Supply Voltage Range, Vpp**.........................-0.6V to +14.0V
Input Voltage Range, All inputs except A9**..-0.6V to +6.5V
A9.....-0.6V to +13.5V
Output Voltage Range**...............................-0.6V to VCC +1V
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
** All voltage values are with respect to GND.
Maximum Operating Case T emperature, TC...................125°C
Storage Temperature Range, T
.....................-65°C to 150°C
stg
RECOMMENDED OPERA TING CONDITIONS
V
V
NOTES:
1. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The deivce must not be inserted into or removed from the
board when VPP or VCC is applied.
2. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be I
Supply Voltage
CC
Supply Voltage
PP
High-level input voltageV
IH
Low-level input voltage
V
IL
Voltage level on A9 for signature mode
V
ID
Operating free-air temperature
T
A
Operating case temperature
T
C
Read Mode
SNAP! Pulse programming algorithm
Read Mode
SNAP! Pulse programming algorithm
1
2
TTL inputs2
CMOS inputs
TTL inputs-0.50.8V
CMOS inputs-0.50.2V
MINTYPMAXUNIT
4.555.5V
6.256.56.75V
-0.6
V
CC
12.751313.25V
V
+1
CC
-0.2VCC+1
V
CC
11.513V
-55°C
+125°C
+ I
.
CC2
PP1
V
V
V
ELECTRICAL CHARACTERISTICS O VER RECOMMENDED RANGES OF SUPPLY V OL TA GE AND
OPERA TING FREE-AIR TEMPERA TURE
1
PARAMETER
High-level output voltage
V
OH
Low-level output voltage
V
OL
Input current (leakage)
I
I
Output current (leakage)
I
O
supply current
V
I
I
I
CC1VCC
I
CC2VCC
I
NOTES:
1. Typical values are at TA=25°C and nominal voltages.
2. This parameter has been characterized at 25°C and is not tested.
SMJ27C256
Rev. 1.0 9/01
PP
PP1
V
PP2
OS
supply current (during program pulse)
PP
supply current (standby)
supply current (active)
Output current (leakage)
2
TTL-Input Level
CMOS-Input Level
'27C256-15
'27C256-17
'27C256-20
'27C256-25
TEST CONDITIONSMIN
IOH = -400µA
IOL = 2.1mA
VI = 0V to 5.5V
VO = 0V to V
VPP = VCC = 5.5V
VPP = 13V
= 5.5V, E\=V
V
CC
= 5.5V, E\=V
V
CC
E\=V
t
cycle
open
CC
IH
CC
, VCC=5.5V
IL
= minimum, outputs
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
2.4V
TYP
3550mA
1525mA
MAXUNIT
0.4V
±1µA
±1µA
10µA
500µA
300µA
100mA
Page 6
UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
CAP A CIT ANCE O VER RECOMMENDED RANGES OF SUPPLY V OL TAGE AND OPERATING
FREE-AIR TEMPERATURE, f = 1MHz*
PARAMETER
C
C
* Capacitance measurements are made on a sample basis only.
** T ypical values are at T
Input capacitance
i
Output capacitance
o
= 25°C and nominal voltages.
A
SWITCHING CHARACTERISTICS O VER RECOMMENDED RANGES OF SUPPLY V OL TAGE
AND OPERA TING FREE-AIR TEMPERATURE
PARAMETER
Access time from address150170ns
t
a(A)
Access time from E\150170ns
t
a(E)
t
en(G)R
Output enable time from G\7070ns
Disable time of output from G\ or E\,
t
dis
whichever occurs first
Output data valid time after change of
t
v(A)
address, E\, or G\, whichever occurs first
TEST CONDITIONSTYP**MAXUNIT
= 0V
V
I
= 0V
V
O
610pF
1014pF
1,2
TEST
CONDITIONS
1, 2
-15
MIN MAX MIN MAX
see Figure 2
3
3
055055 ns
00 ns
-17
UNIT
PARAMETER
Access time from address200250300ns
t
a(A)
Access time from E\200250300ns
t
a(E)
t
en(G)R
NOTES:
1.Timing measurements are made at 2V for logic high and 0.8V for logic low (see figure 2).
2. Common test conditions apply for t
3. V alue calculated from 0.5V delta to measured output level. This parameter is only sampled and not 100% tested.
Output enable time from G\75100120ns
Disable time of output from G\ or E\,
t
dis
whichever occurs first
Output data valid time after change of
t
v(A)
address, E\, or G\, whichever occurs first
3
except during programming.
dis
3
TEST
CONDITIONS
see Figure 2
1, 2
-20-25
MIN MAX MIN MAX MIN MAX
0600600105ns
000 ns
-30
UNIT
SWITCHING CHARACTERISTICS FOR PROGRAMMING: VCC = 6.5V and VPP = 13V (SNAP!
Pulse), TA = 25°C
MINMAXUNIT
t
dis(G)
t
en(G)W
PARAMETER
Output disable time from G\0130ns
Output enable time from G\150ns
SMJ27C256
Rev. 1.0 9/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Page 7
UVEPROM
SMJ27C256
Austin Semiconductor, Inc.
RECOMMENDED TIMING REQUIREMENTS FOR PROGRAMMING: VCC = 6.5 and VPP = 13
(SNAP! Pulse), TA = 25°C (See Figure 2)
MINTYPMAXUNIT
t
h(A)
t
h(D)
t
w(E)PR
t
su(A)
t
su(G)
t
su(E)
t
su(D)
t
su(VPP)
t
su(VCC)
Hold Time, Address
Hold Time, Data
Pulse Duration, Initial Program
Setup Time, Address
Setup Time, G\
Setup Time, E\
Setup Time, Data
Setup Time, V
Setup Time, V
PP
CC
0µs
2µs
95100105µs
2µs
2µs
2µs
2µs
2µs
2µs
P ARAMETER MEASUREMENT INFORMA TION
2.08V
RL = 800Ω
Output Under Test
CL = 100 pF
NOTES:
1. CL includes probe and fixture capacitance.
1
The AC testing inputs are driven at 2.4V for logic high and 0.4V for logic low . Timing measurements are
made at 2V for logic high and 0.8V for logic low for both inputs and outputs.
SMJ27C256
Rev. 1.0 9/01
FIGURE 2. LOAD CIRCUIT AND VOLTAGE WAVEFORMS
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.
SMJ27C256
Rev. 1.0 9/01
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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