Datasheet SMD HC 93 Datasheet (FREI)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT93

4-bit binary ripple counter

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

FEATURES

• Various counting modes

• Asynchronous master reset

• Output capability: standard

• ICC category: MSI

divide-by-two section and a divide-by-eight section. Each section has a separate clock input (

CP0 and CP1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q

n

outputs do not occur simultaneously because of internal ripple delays.

GENERAL DESCRIPTION

The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a

Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops.

Since the output from the divide-by-two section is not internally connected to the succeeding stages,

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C C

I PD

/ t

PLH

propagation delay CP0 to Q maximum clock frequency 100 77 MHz

0

CL= 15 pF; VCC=5 V

input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 22 22 pF

the device may be operated in various counting modes. In a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8 and 16 are performed at the Q0, Q1, Q2 and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4 and 8 are available at the Q1, Q and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

TYPICAL

UNIT

HC HCT

12 15 ns

2

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz; fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF; VCC= supply voltage in V

2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 2, 3 MR 4, 6, 7, 13 n.c. not connected 5V 10 GND ground (0 V) 12, 9, 8, 11 Q 14

CP

1

CC

to Q

0

, MR

1

clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered)

2

asynchronous master reset (active HIGH)

positive supply voltage

3

ﬂip-ﬂop outputs clock input 1st section (HIGH-to-LOW, edge-triggered)

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

FUNCTION TABLE

Fig.4 Functional diagram.

COUNT

Q

0

0 1 2 3

4 5 6 7

8 9 10 11

12 13 14 15

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Notes

1. Output Q

connected to CP1.

0

H = HIGH voltage level L = LOW voltage level

OUTPUTS

Q

1

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Q

2

3

L L L L

H H H H

Fig.5 Logic diagram.

December 1990 4

MODE SELECTION

RESET

INPUTS

MR2Q0Q1Q2Q

MR

1

H

LLLL

L

H

L

OUTPUTS

3

count count count

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

THL

t

rem

t

W

t

W

f

max

/ t

propagation delay

PLH

CP0 to Q

propagation delay

PLH

CP1 to Q

propagation delay

PLH

CP1 to Q

propagation delay

PLH

CP1 to Q

0

1

2

3

propagation delay

MRn to Q

output transition time 19

TLH

n

removal time

MRn to CP0, CP

1

pulse width

CP0, CP

1

master reset pulse width

MR

n

maximum clock pulse

frequency CP0, CP

1

(°C)

T

amb

74HC

min. typ. max. min. max. min. max.

41

50 10 9

80 16 14

6.0 30 35

15 12

49 16 13

61 22 18

80 29 23

50 18 14

7 6

8 3 2

14 5 4

30 91 108

125 25 21

135 27 23

185 37 31

245 49 42

155 31 26

75 15 13

65 13 11

100 20 17

4.8 24 28

155 31 26

170 34 29

230 46 39

305 61 52

195 39 33

95 19 16

190 38 32

205 41 35

280 56 48

370 71 63

235 47 40

110 22 19

75 15 13

120 24 20

4.0 20 24

.

UNIT

ns 2.0

MHz 2.0

TEST CONDITIONS

V

CC

WAVEFORMS+25 −40 to +85 −40 to +125

(V)

Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.6

4.5

6.0

December 1990 5

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

CP0, CP MR

n

0.60

1

0.40

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

T

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V

CC

(V)

min. typ. max. min. max. min. max.

t

PHL

t

PHL

t

PHL

t

PHL

t

PHL

t

THL

/ t

propagation delay

PLH

CP0 to Q

propagation delay

PLH

CP1 to Q

propagation delay

PLH

CP1 to Q

propagation delay

PLH

CP1 to Q

0

1

2

3

propagation delay

MRn to Q

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

n

18 34 43 51 ns 4.5 Fig.6

24 46 58 69 ns 4.5 Fig.6

30 58 73 87 ns 4.5 Fig.6

17 33 41 50 ns 4.5 Fig.7

WAVEFORMS+25 −40 to +85 −40 to +125

t

rem

t

W

t

W

f

max

removal time

MRn to CP0, CP

1

pulse width

CP0, CP

1

master reset pulse width

MR

n

maximum clock pulse

10 3 13 15 ns 4.5 Fig.7

16 7 20 24 ns 4.5 Fig.6

16 5 20 24 ns 4.5 Fig.7

30 70 24 20 MHz 4.5 Fig.6 frequency CP0, CP

1

December 1990 6

Philips Semiconductors Product speciﬁcation

4-bit binary ripple counter 74HC/HCT93

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.6 Waveforms showing the clock (CPn) to output (Qn) propagation delays, the clock pulse width, output

transition times and the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the master reset (MRn) pulse width, the master reset to output (Qn) propagation

delays and the master reset to clock (CPn) removal time.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

December 1990 7