Datasheet SM8701BM Datasheet (NPC)

SM8701BM

NIPPON PRECISION CIRCUITS INC.

DVD Player Clock Generator

OVERVIEW

The SM8701BM is a 27 MHz master clock, 5-system output clock generator for DVD players. It has 2 built-in
PLLs that, with the addition of a single crystal oscillator element, can generate 256fs, 384fs and 768fs clocks
plus independent fixed-frequency 27 MHz and 33.8688 MHz output clocks. Supported sampling frequencies
(fs) include the standard 32, 44.1 or 48 kHz, or double-frequency 64, 88.2 or 96 kHz.

FEATURES

■

27 MHz master clock (internal PLL reference
clock)

■

Generated clocks

• 27 MHz output

• 33.8688 MHz output

• 256fs output

• 384fs output

• 768fs output

■

Sampling frequency fs

• 32/64 kHz

• 44.1/88.2 kHz

• 48/96 kHz

■

Low jitter output

■

3-wire serial or parallel control

■

Supply voltage: V

■

20-pin SSOP package

V

DD
DDO

= V

= V

DDP

DD3

= 5.0V

= 3.3V

PINOUT

(T op V iew)

MLEN/R2

GNDP
VDDP SO4

VDD3

1

P/S
VDD
GND

XTO

XTI

10 11

MO

SM8
701

B

20

MCK/R1
MDT/R0
RSTN
SO3
VDDO
GNDO
SO2

SO1
MON

APPLICATIONS

■

DVD players

ORDERING INFORMATION

De vice Pack ag e

SM8701BM 20-pin SSOP

PACKAGE DIMENSIONS

(Unit: mm)

7.40MAX

7.20 0.05

7.90 0.20

5.30 0.05

1.80 0.10

0.10 0.10

2.10MAX

0.68 0.12

0.65

0.10

0.30 0.10

NIPPON PRECISION CIRCUITS—1

0.13

M

0.62TYP

1.30 0.10

0.20 0.05

0.6 0.15

0 to 8

BLOCK DIAGRAM

SM8701BM

XTI

XTO

P/S

MLEN/R2

MDT/R0

MCK/R1

Oscillator

External
Interface

Divider0

Divider1

Phase

Comparator0

Divider0

Phase

Comparator1

Divider1

Charge
Pump0

Charge
Pump1

LPF0 VCO0

SO4

SO3

Divider

SO2

SO1

LPF1 VCO1

MO

MON

RSTN

Reset

Circuits

NIPPON PRECISION CIRCUITS—2

SM8701BM

PIN DESCRIPTION

Number Name I/O Description

Control signal input.

1

1 MLEN/R2 Ip

2 P/S Ip

3 V DD – 5 V supply (Digital block)
4 GND – Ground (Digital block)
5 X T O O Reference signal cr ystal oscillator element connection
6 X TI I R eference signal cr ystal oscillator element connection or external clock input
7 GNDP – Ground (PLL block)
8 VDDP – 5 V supply (PLL block)

9 VDD3 – 3.3 V supply (output buffer)
10 MO O 27 MHz fixed-frequency output
11 MO N O 27 MHz fixed-frequency output (inverted)
12 SO 1 O 33.8688 MHz fixed-frequency output
13 S O 4 O 768fs output
14 S O 2 O 256fs output
15 GNDO – Ground (output buffer)
16 VDDO – 3.3 V supply (output buffer)
17 S O 3 O 384fs output
18 RSTN Ip

19 MDT/R0 Ip

20 MCK/R1 Ip

1. Schmitt trigger input with pull-down resistor

2. Schmitt trigger input with pull-up resistor

In serial mode: latch enable signal
In parallel mode: sampling rate select signal

Mode select signal.

1

LO W : serial mode, HIGH: parallel mode

2

L O W -level reset input
Control signal input.

1

In serial mode: control data input signal
In parallel mode: sampling frequency select signal

Control signal input.

1

In serial mode: clock signal
In parallel mode: sampling frequency select signal

NIPPON PRECISION CIRCUITS—3

+

+

−

−

−

−

° C

SPECIFICATIONS

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit

V

Supply voltage range

Supply voltage deviation

Input voltage range V
Output voltage range V
Po w er dissipation P
Storage temperature range T

DD

V

DDO

V

DD

V

DDO

GND – GNDP,

GND – GNDO,

GNDP – GNDO

– V

, V

, V

– V

IN

OUT

D

stg

−

°

DDP

DD3

DDP

DD3

,

,

,

Digital inputs
Digital outputs

SM8701BM

0.3 to 6.5 V

±0.1 V

0.3 to V

0.3 to V

0.3 V

DD

, V

DDO

0.3 V

DD3

300 m W

55 to 125

Recommended Operating Conditions

Parameter Symbol Condition Rating Unit

V

, V

DDO

Supply voltage ranges

Operating temperature range T

DD3

V

, V

DD

DDP

opr

2.7 to 3.6 V

4.5 to 5.5 V
40 to 85

C

NIPPON PRECISION CIRCUITS—4

DC Electrical Characteristics

−

°

×

×

−

−

−

−

SM8701BM

External clock, T

= − 40 to 85 ° C, V

a

DD

= V

= 4.5 to 5.5 V, V

DDP

stated

Parameter Symbol Condition

All supplies.
V

= V

DD

V

DDO

T

Current consumption I

DD

a

using XTI external 27 MHz
master clock, no load on
clock outputs (MO, MON,
SO1 to SO4)

HIGH-level input voltage V

L O W -level input voltage V

HIGH-level input voltage V
L O W -level input voltage V
HIGH-level input current
L O W -level input current
HIGH-level input current
L O W -level input current

1

1

2

2

HIGH-level input current I
L O W -level input current I
HIGH-level output voltage V
L O W-level output voltage V

I
I
I
I

IH1

IL1

IH2

IL2

IH1

IL1

IH2

IL2

IH3

IL3

OH

OL

P/S, MLEN/R2, MCK/R1,
MDT/R0, RSTN

P/S, MLEN/R2, MCK/R1,
MDT/R0, RSTN

XTI 0.7
XTI – – 0.3
V

IN

V

IN

V

IN

V

IN

XTI, V
XTI, V
All outputs. I
All outputs. I

1. P/S, MLEN/R2, MCK/R1, MDT/R0. Schmitt trigger input, internal pull-down.

2. RSTN. Schmitt trigger input, internal pull-up.

= 5.0V,

DDP

= V

DD3

= 25

C, fs = 48 kHz,

= V

DD

= 0 V – –
= V

DD

= 0 V – –

= V

IN

DD

= 0 V – –

IN

OH

OL

DDO

= V

= 2.7 to 3.6 V unless otherwise

DD3

Rating

min typ max

= 3.3 V,

–3245mA

2.0 – – V

– – 0.8 V

V

DD

––V

V

DD

– – 150 µA

1µA

––1µA

150 µA

––40µA

40 µA

=

2 mA V

0.4 – – V

DDO

= 4 mA – – 0.4 V

Unit

V

NIPPON PRECISION CIRCUITS—5

PLL AC Electrical Characteristics

SM8701BM

°

Ω

External clock, T

= − 40 to 85 ° C, V

a

stated

Parameter Symbol Condition

XTI external input clock frequency f

Output clock rise time t

Output clock fall time t

MO, MON output clock jitter
SO1, SO2 (Standard), SO3, SO4

output clock jitter

1

SO2 (Double) output clock jitter

MO, MON output clock duty

SO1, SO2 (Standard), SO3, SO4
output clock duty

1

SO2 (Double) output clock duty
Settling time t
Power-up time

2

RSTN external reset LOW -level
pulsewidth

1. 1.4V to 1.4V. Ta=20
NPC’s standard crystal oscillator: R = 10.5
measurement apparatus: HP4195
Load capacitance: C1 = 7 pF, C2 = 11 pF

1

1

1

1

C. The characteristics of output clock jitter and output clock duty depends on cr ystal oscillator.

DD

M

R

F

JITTER

= V

= 4.5 to 5.5 V, V

DDP

DUTY: 50 ± 5% – 27.0000 – MHz
All outputs, 0.2 to 0.8V

or V

, C

= 20 pF

DD3

L

All outputs, 0.8 to 0.2V
or V

, C

= 20 pF

DD3

L

Standard tolerance
Cr ystal oscillator element

Cr ystal oscillator element,
C

= 20 pF

L

DUTY

S

t

P

t

RSTL

C

= 20 pF 40 50 60 %

L

C

= 20 pF 23.3 33.3 43.3 %

L

All outputs – – 40 m s
All outputs – – 50 m s

1.4 V to 1.4 V 10 0 – – ns

, L = 5.38 mH, Ca = 6.74 fF, Cb = 1.85 pF

DDO

DDO

DDO

= V

= 2.7 to 3.6 V unless otherwise

DD3

Rating

min typ max

– 2.5 – ns

– 2.5 – ns

– 150 – ps

– 150 – ps

– 450 – ps

45 50 55 %

Unit

Cb

L

Ca R

2. Time from OFF condition to stable frequency output.

NIPPON PRECISION CIRCUITS—6

Serial Interface AC Characteristics

SM8701BM

External clock, T

= − 40 to 85 ° C, V

a

DD

= V

= 4.5 to 5.5 V, V

DDP

DDO

= V

= 2.7 to 3.6 V unless otherwise

DD3

stated

Parameter Symbol Condition

MCK HIGH-level pulsewidth t
MCK LOW-level pulsewidth t
MCK pulse cycle time t
MDT setup time t
MDT hold time t
MLEN setup time
MLEN hold time
MLEN HIGH-level pulsewidth t
MLEN LOW-level pulsewidth t

1. Time from the MLEN falling edge to the next MCK rising edge. If the MCK clock stops after the LSB, the MLEN rise timing is optional.

2. Time from MCK rising edge corresponding to the LSB to the MLEN rising edge.

1

2

MCWH

MCWL

MCY

MDS

MDH

t

MLS

t

MLH

MHH

MLL

min typ max

40 – – ns
40 – – ns

100 – – ns

40 – – ns
40 – – ns
40 – – ns
40 – – ns

200 – – ns

16 × t

MCY

tMCWLtMCWH

Rating

––ns

tMLH tMLS

Unit

MCK

MDT

MLEN

tMCY

MSB LSB

tMLS

tMDHtMDS

tMLL

1.4V

1.4V

tMHH

1.4V

NIPPON PRECISION CIRCUITS—7

FUNCTIONAL DESCRIPTION

27 MHz Master Clock

SM8701BM

The 27 MHz master clock is generated either by con­necting a crystal oscillator element between XTI (pin

6) and XTO (pin 5), as shown in figure 1, or by con-

necting an external 27 MHz clock to XTI, as shown

C2

C1

C1, C2 = 5 to 33pF

XTO (Pin5)

Oscillator

XTI (Pin6)

SM8701BM

Figure 1. Crystal oscillator connection

in figure 2. Input 27MHz master clock on XTI when
using an external clock. Crystal oscillator element
must be fundamental.

Internal
Circuits

MO (Pin10)

MON (Pin11)

Open

External Clock

XTO (Pin5)

XTI (Pin6)

SM8701BM

Oscillator

Figure 2. External clock input

Internal
Circuits

MO (Pin10)

MON (Pin11)

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SM8701BM

Sampling Frequency and Output Clock Frequency

The SM8701BM generates several output clocks
from the 27 MHz master clock, with frequencies of
256fs (SO2), 384fs (SO3) and 768fs (SO4), where fs
is the sampling frequency selected by external con-

Table 1. Sampling frequency and output clock frequency

Sampling rate

Standard

Double

Sampling

frequency fs

32 kHz 33.8688 8.192 12.288 24.576

44.1 kHz 33.8688 11.2896 16.9344 33.8688
48 kHz 33.8688 12.288 18.432 36.864
64 kHz 33.8688 16.384 24.576 24.576

88.2 kHz 33.8688 22.5792 33.8688 33.8688
96 kHz 33.8688 24.576 36.864 36.864

SO1 SO2 SO3 SO4

Reset

The SM8701BM supports an external reset using
RSTN (pin 18). At reset, the mode register takes its
default value, and the output clocks have default fre­quencies.

trol inputs. SO1 outputs 33.8688 MHz clock. The
supported sampling frequencies and the output clock
frequencies are shown in table 1.

Output clock frequency (MHz)

When RSTN goes HIGH, an internal reset continues
for a period of 1024 cycles of the 27 MHz master
clock. The timing is shown in figure 3.

RSTN

Internal Reset

Master Clock

Reset

1 2 3 1024

1024 Master Clock

Figure 3. External reset timing

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Operation Control

SM8701BM

The SM8701BM functions are controlled by inputs
MLEN/R2 (pin 1), MDT/R0 (pin 19) and MCK/R1
(pin 20). The operating mode is selected by input P/S
(pin 2)—serial control when P/S is LOW, and paral­lel control when P/S is HIGH. Table 2 shows the
relationship between functions and mode.

Serial control (P/S = LOW)

When P/S is LOW, the control interface is serial con­trol mode. The serial control data is set by 16-bit
MDT data in sync with the MCK clock and the

MCK

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MDT

Table 2. Control functions

Controllable

Function

Serial Parallel

Sampling frequency group: 48/44.1/32 kHz Yes Yes
Sampling rate: standard/double Yes Yes
Clock output: enable/disable Yes No

MLEN enable signal clock at the serial control
mode. The format is shown in figure 4.

MLEN

Figure 4. Serial control format

The 16-bit mode register (MREG) is shown in figure
5, and the name and function of each bit is described
in tables 3 to 5. In serial control mode, mode register

0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 R2 R1 R0MREG

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 5. Mode register

Table 3. Mode register control bit functions

Bit Name Function

D9 CE6 MON output enable/disable
D8 C E5 MO output enable/disable
D7 C E 4 SO4 output enable/disable
D6 C E 3 SO3 output enable/disable

bits D15 to D10 must be set to 011100. D3 is fixed as
LOW.

RSV

Note: RSV is fixed as LOW .

Table 4. CE6 to CE1 clock output control setting

CE6 to CE1 Clock output

LO W Disable (LOW -level output)

HIGH Enable (default)

D5 C E 2 SO2 output enable/disable
D4 C E 1 SO1 output enable/disable
D3 RS V Fixed as LOW

D2/D1/D0 R2/R1/R0 Sampling frequency select

NIPPON PRECISION CIRCUITS—10

SM8701BM

Table 5. Sampling frequency select (R2, R1, R0)

R2 R 1 R0 Sampling rate Sampling frequency group Sampling frequency

LO W LOW LO W Standard 48 kHz 48 kHz (default)
LOW LOW HIGH Standard 44.1 kHz 44.1 kHz
LOW HIGH LOW Standard 32 kHz 32 kHz
LOW HIGH HIGH Prohibited (test mode)
HIGH L OW LOW Double 48 kHz 96 kHz
HIGH L OW HIGH Double 44.1 kHz 88.2 kHz
HIGH HIGH LOW Double 32 kHz 64 kHz
HIGH HIGH HIGH Prohibited (test mode)

When the sampling frequency is changed, a settling
time of 40 ms (max) is required to make the output
frequency stable. The SO2 to SO4 output response

MLEN

SO2 to 4

SO1

Figure 6. System clock transient timing

when the frequency is changed is shown in figure 6.
SO1 fixed on 33.8688 MHz.

tS

Clock Transition Region

33.8688MHz

NIPPON PRECISION CIRCUITS—11

Parallel control (P/S = HIGH)

SM8701BM

When P/S is HIGH, the control interface is parallel
control mode. The parallel control pins R2 (pin 1),

Table 6. Sampling frequency select (R2, R1, R0)

R2 R 1 R0 Sampling rate Sampling frequency group Sampling frequency

LO W LOW LO W Standard 48 kHz 48 kHz (default)
LOW LOW HIGH Standard 44.1 kHz 44.1 kHz
LOW HIGH LOW Standard 32 kHz 32 kHz
LOW HIGH HIGH Prohibited (test mode)
HIGH L OW LOW Double 48 kHz 96 kHz
HIGH L OW HIGH Double 44.1 kHz 88.2 kHz
HIGH HIGH LOW Double 32 kHz 64 kHz
HIGH HIGH HIGH Prohibited (test mode)

Note that in parallel control mode, clock output
enable/disable controls are not available. Also note

R1 (pin 20) and R0 (pin 19) and functions are shown
in table 6.

frequency group or sampling rate select settings (it is
determined by R2, R1, R0 condition).

that the reset function does not affect the sampling

NIPPON PRECISION CIRCUITS—12

TYPICAL APPLICATION

+5V

+3.3V

SM8701BM

CPU

C3

C2

C4

C1

MLEN/R2

P/S

VDD

GND

XTO

X'tal

XTI

GNDP

VDDP

VDD3

C5

MO

MCK/R1

MDT/R0

RSTN

SO3

VDDO

GNDO

SO2

SO4

SO1

MON

SM8701BM

■ Connect the decoupling capacitors (approximately

0.1µF and 1000pF) in parallel, as close to power
supply pins as possible.

■ In order to minimize noise, it is useful to make

ground as solid pattern.

■ Master clock stability affects the other outputs sta-

bility. In the usage of crystal oscillator, load
capacitor and crystal oscillator should be placed as
close to the SM8701BM as possible, and wired
shortly. Select crystal oscillators and load capaci­tance carefully, depending on the condition, as
those combination will have influence on the fre­quency accuracy(C1, C2).

■ Supply pattern including decoupling capacitors

needs careful attention to make the IC’s perfor­mance better, since the SM8701BM outputs sev­eral high frequency clocks. Pattern capacitance
from output pins should not to be large for preven­tion of the noise. Connecting output pins to buff­ers is useful if it is necessary.

384fs

256fs

C6

768fs

33.8688MHz

27MHz(Inverted)

27MHz

■ Power supply and ground pins.

• VDD :5V Power supply for digital block
(CPU I/F*, XT1, XT2).

• GND : Ground for digital block
(CPU I/F*, XT1, XT2, output

block except SO3).

• VDDP :5V Power supply for PLL block.

• GNDP : Ground for PLL block.

• VDDO :3.3V Power supply for SO3.

• GNDO : Ground for SO3.

• VDD3 :3.3V Power supply for output block
(except SO3).

*: CPU I/F: MDT/R0, MCK/R1, MLEN/R2, RSTN,

P/S

NIPPON PRECISION CIRCUITS—13

SM8701BM

NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.

NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome

Koto-ku, Tok yo 135-8430, Japan

NIPPON PRECISION CIRCUITS INC.

Telephone: [phone]
Facsimile: 03-3642-6698

NC9822BE 2000.1

NIPPON PRECISION CIRCUITS—14