Datasheet SM5882AS, SM5883AS, SM5883BS, SM5885CS Datasheet (NPC)

Page 1
Σ
Σ∆
Σ∆
DECO SM588 × series
Audio 3rd-order Σ∆ D/A Converter
OVERVIEW
The Σ DECO SM588 × series, fabricated using NPC’s Molybdenum-gate CMOS process, are D/A converter ICs for digital audio, that provide all the basic converter functions in miniature 8-pin packages. They each feature built-in 8-times oversampling digital filter, Σ∆ jitter-compensated D/A converter, and post-analog lowpass fil­ter converter stages required for digital audio. They can sample at up to 96kHz for 16 or 24-bit input word length. A type with built-in deemphasis filter is also available for applications requiring deemphasis.
FEATURES
3-wire Input
2-channel stereo configuration
256fs, 384fs, or 512fs system clock (applied by product / version)
Input format 3-wire serial, MSB first, rear-packed 16 or 24-bit (applied by product / version)
8-times oversampling digital filter
• 32 dB stopband attenuation
• ±0.05 dB passband ripple
2-channel D/A converter
• 3rd-order noise shaper
• Oversampling operation
3rd-order post-analog lowpass filter
4.5 to 5.5 V supply voltage
8-pin SOP
Molybdenum-gate CMOS process
2-wire Input with Deemphasis Filter
2-channel stereo configuration
256fs, 384fs, or 512fs system clock (applied by product / version)
Input format 2-wire serial, MSB first, rear-packed 16 or 24-bit (applied by product / version)
Deemphasis filter (fs = 44.1 kHz sample rate)
8-times oversampling digital filter
• 32 dB stopband attenuation
• ±0.05 dB passband ripple
2-channel D/A converter
• 3rd-order noise shaper
• Oversampling operation
3rd-order post-analog lowpass filter
4.5 to 5.5 V supply voltage
8-pin SOP
Molybdenum-gate CMOS process
APPLICATIONS
Audio equipment
PINOUTS
3-wire input 2-wire input with built-in deemphasis filter
CLK
1
4
5 88
8
5
DATA
BCKI
LRCI
ORDERING INFORMATION
Device Package
SM5882AS
SM5883AS
SM5883BS
SM5885CS
LO
VDD
VSS
RO
8-pin SOP
DATA
DEEM
LRCI
CLK
1
5 88
4
NIPPON PRECISION CIRCUITS—1
LO
8
VDD
VSS
RO
5
Page 2
PACKAGE DIMENSIONS
(Unit : mm)
Weight : 0.07g
SM588 × series
4.4 0.2
6.2 0.3
0.15
+
0.05
0.1
0.4 0.2
0.695typ
5.2 0.3
0.05 0.05
1.5 0.1
1.27
0.10
0.4 0.1
0.12
M
SERIES LINEUP
Device Input length Type Pin 2 function Master clock
SM5882AS 16 2-wire input Deemphasis control 384fs
SM5883AS 16 3-wire input Bit clock input 384fs
SM5883BS 16 3-wire input Bit clock input 256fs
SM5885CS 24 3-wire input Bit clock input 512fs
0 to 10
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Page 3
BLOCK DIAGRAM
LRCI DATA
SM588 × series
CLK
Timing
control
9 Level
DEM DAC
9 Level
DEM DAC
Input interface
LR
Filter & attenuation
operation block
LR
Noise shaper
operation block
9 Level
DEM DAC
BCKI*
DEEM**
9 Level
DEM DAC
+
LO VSS RO
* : Not available for 2-wire input type ** : Not available for 3-wire input type
VDD
+
PIN DESCRIPTION
Number Name I/O Description
1 DATA I Serial data input
1
2
3 LRCI I Sample rate (fs) clock input. Left-channel input when HIGH, and right-channel input when LOW.
4 CLK I External clock input
5 RO O Right-channel analog output
6 VSS Ground
7 VDD Supply
8 LO O Left-channel analog output
BCKI
DEEM
2
I Bit clock input
I Deemphasis ON/OFF control (44.1 kHz, ON when HIGH)
1. 3-wire type
2. 2-wire type with built-in deemphasis filter
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Page 4
SM588 × series
SPECIFICATIONS
Absolute Maximum Ratings
V
= 0 V
SS
Parameter Symbol Rating Unit
Supply voltage range V
Input voltage range
Storage temperature range T
Power dissipation P
1. All inputs Also applicable during supply switching.
Recommended Operating Conditions
1
+
°
° C
0.3 to 7.0 V
V
SS
0.3 to V
0.3 V
DD
55 to 125
300 mW
C
V
STG
DD
IN
D
V
= 0 V
SS
Parameter Symbol Rating Unit
Supply voltage V
Operating temperature T
DD
OPR
DC Characteristics
V
= 4.5 to 5.5 V, V
DD
Parameter Symbol Condition
Current consumption
1
CLK HIGH-level input voltage V
CLK LOW-level input voltage V
CLK AC-coupled input voltage V
HIGH-level input voltage
LOW-level input voltage
CLK HIGH-level input current I
CLK LOW-level input current I
Input leakage current
1. V
= 5 V, CLK clock input frequency f
DD
Input data: NPC pattern.
2
2. Pins BCKI (3-wire type), DEEM (2-wire type with deemphasis filter), DATA, LRCI
= 0 V, Ta = 40 to 85 ° C
SS
2
2
V
= 16.9344 MHz (384fs type)/11.2896 MHz (256fs type)/22.5792MHz (512fs type), no output load.
CLK
I
DD
INAC
V
I
LH
I
IH1
IL1
IH2
IL2
IH
IL
LL
Clock input 0.7V
Clock input 0.3V
V
= V
IN
DD
V
= 0 V 20 62 170 µA
IN
V
= V
IN
DD
V
= 0 V 1.0 µA
IN
4.5 to 5.5 V
40 to 85
Rating
min typ max
12.5 25.0 mA
DD
––V
DD
0.7 V
0.5V
DD
0.2V
––V
DD
20 62 170 µA
1.0 µA
Unit
V
p-p
V
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Page 5
AC Digital Characteristics
V
= 4.5 to 5.5 V, V
DD
System clock (CLK)
256fs type
= 0 V, Ta = 40 to 85 ° C
SS
SM588 × series
Parameter Symbol
HIGH-level clock pulsewidth t
LOW-level clock pulsewidth t
Clock pulse cycle t
384fs type
Parameter Symbol
HIGH-level clock pulsewidth t
LOW-level clock pulsewidth t
Clock pulse cycle t
512fs type
Parameter Symbol
HIGH-level clock pulsewidth t
LOW-level clock pulsewidth t
Clock pulse cycle t
CWH
CWL
XI
CWH
CWL
XI
CWH
CWL
XI
Rating
Unit
min typ max
20.0 125 ns
20.0 125 ns
40.0 250 ns
Rating
Unit
min typ max
13.15 125 ns
13.15 125 ns
26.3 250 ns
Rating
Unit
min typ max
10 125 ns
10 125 ns
20 250 ns
CLK
t
CWL
V
IH1
0.5V
DD
V
t
CWH
t
XI
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IL1
Page 6
Serial inputs
3-wire type (BCKI, DATA, LRCI)
SM588 × series
ns
Parameter Symbol
BCKI HIGH-level pulsewidth t
BCKI LOW-level pulsewidth t
BCKI pulse cycle t
DATA setup time t
DATA hold time t
LRCI edge to first BCKI rising edge t
Last BCKI rising edge to LRCI edge t
BCKI
t
BCWH
t
BCWL
t
BCY
DATA
t
DS
LRCI
t
LB
2-wire type (DATA, LRCI)
t
DH
BCWH
BCWL
BCY
DS
DH
LB
BL
Rating
min typ max
Unit
50.0 ns
50.0 ns
1/(64fs) ns
50.0 ns
50.0 ns
50.0 ns
50.0 ns
V
0.35
DD
V
0.35
DD
V
0.35
DD
t
BL
Parameter Symbol Condition
DATA setup time t
DATA hold time t
LRCI edge to internal BCLK rising edge t
DS
DH
256fs/512fs 1.5t
LB
384fs 3.5t
Internal
BCLK
t
DS
DATA
LRCI
t
LB
Control input (DEEM: 2-wire type)
Parameter Symbol
Rise time t
Fall time t
Rating
min typ max
Unit
50 ns
50 ns
XI
XI
2.5t
4.5t
XI
XI
0.35
t
DH
0.35
0.35
Rating
min typ max
r
f
50 ns
50 ns
ns
V
DD
V
DD
V
DD
Unit
DEEM
0.5VDD
tf tr
0.2VDD
0.5VDD
0.2VDD
0.35V
DD
NIPPON PRECISION CIRCUITS—6
Page 7
SM588 × series
AC Analog Characteristics
256fs type specication (SM5883BS) : VSS = 0 V, VDD = 5 V, 16-bit input type, crystal oscillator frequency f
= 11.2896 MHz, Ta = 25 °C
OSC
Parameter Symbol Condition
Total harmonic distor tion THD + N 1 kHz, 0 dB 0.0035 0.0130 %
LSI output level V
Evaluation board output level V
Dynamic range D.R 1 kHz, 60 dB 90.4 96.4 dB
Signal-to-noise ratio S/N 1 kHz, 0dB/ −∞ 92.8 98.8 dB
Channel separation Ch. Sep 1 kHz, −∞ 0dB 87.5 93.5 dB
Note: These parameters are measured using the measurement block diagram (page 8) and the measurement circuit (page 9).
OUT1
OUT2
1 kHz, 0 dB 1.09 V
1 kHz, 0 dB 1.33 V
min typ max
Rating
384fs type specication (SM5882AS, SM5883AS) : VSS = 0 V, VDD = 5 V, DEEM = 0 V (2-wire type), 16-bit input type, crystal oscillator frequency f
Parameter Symbol Condition
Total harmonic distor tion THD + N 1 kHz, 0 dB 0.003 0.0120 %
LSI output level V
Evaluation board output level V
Dynamic range D.R 1 kHz, 60 dB 90.4 96.4 dB
Signal-to-noise ratio S/N 1 kHz, 0dB/ −∞ 93.0 99.0 dB
Channel separation Ch. Sep 1 kHz, −∞ 0dB 88.5 94.5 dB
OUT1
OUT2
= 16.9344 MHz, Ta = 25 °C
OSC
Rating
min typ max
1 kHz, 0 dB 1.09 V
1 kHz, 0 dB 1.33 V
Unit
rms
rms
Unit
rms
rms
Note: These parameters are measured using the measurement block diagram (page 8) and the measurement circuit (page 9).
512fs type specication (SM5885CS) : VSS = 0 V, VDD = 5 V, 24-bit input type, crystal oscillator frequency f
Parameter Symbol Condition
Total harmonic distor tion THD + N 1 kHz, 0 dB 0.0035 0.0130 %
LSI output level V
Evaluation board output level V
Dynamic range D.R 1 kHz, 60 dB 92.0 98.0 dB
Signal-to-noise ratio S/N 1 kHz, 0dB/ −∞ 92.8 98.8 dB
Channel separation Ch. Sep 1 kHz, −∞ 0dB 87.5 93.5 dB
Note: These parameters are measured using the measurement block diagram (page 8) and the measurement circuit (page 9).
= 22.5792MHz, Ta = 25 °C
OSC
OUT1
OUT2
1 kHz, 0 dB 1.09 V
1 kHz, 0 dB 1.33 V
Rating
min typ max
Unit
rms
rms
NIPPON PRECISION CIRCUITS—7
Page 8
AC analog measurement block diagram
256fs/384fs
CLK
BCLK*
LRCK(fs)
fs= 44.1kHz
/512fs
SM588× series
Evaluation
Board
NF Corporation
CD Player
EVA. Filter3346A
*Not available for 2-wire type
Serial Interface Adaptor
corresponds to SIA-2322
DATA= 16/24bit
Left
Channel
100k Input Impedance
Audio Precision System Two
corresponds to SYS-2322
Right Channel
AC analog measurement conditions
Parameter
Total harmonic distor tion THD + N
Dynamic range D.R D-RANGE
Signal-to-noise ratio S/N Not used
Channel separation Ch. Sep Not used 20 kHz lowpass filter
1. Pins LO and RO should have an output load of 10 k (min).
1
Symbol
OUT
3346A left/right-channel selector
switch
Not used
Audio Precision System Two audio
analyzer with built-in filter
20 kHz lowpass filter Output level V
22 kHz lowpass filter A-WTD
NIPPON PRECISION CIRCUITS—8
Page 9
AC analog measurement circuit
SM588× series
33k
68p
22k
L ch. OUT
100
+−
2.2u
1
8
NJM
2100
+
2
27k 33k
−+
−+
33u 33u
100p
100k
VCC
+
470u
VEE
R ch. OUT
100
2.2u
+−
100p
100k
0.1u
22k
7
NJM
685
27k 33k
−+
33u 33u
2100
+
−+
22k
+
33u
330p
33u
+
22k
3
+
68p
33k
33u
330p
0.01u
LO
DATA
SM5882/83/85
VSS
VDD
BCKI
/DEEM
LRCI
LRCI
DATA
BCKI/DEEM
CLK
RO
CLK
11
10
−+
X'tal
6
10p10p
1
100u
16.9344MHz(384fs)
2
3
VDD VSS
11.2896MHz(256fs)
22.5792MHz(512fs)
Ext. CLK
0.01u
13
14
12
3
7
4
9
8
56
0.01u
1M
74HCU04
1
2
5
Int. CLK
4
NIPPON PRECISION CIRCUITS—9
Page 10
Theoretical Filter Characteristics
Overall characteristics
SM588× series
Parameter
Passband ripple 0 to 0.4535fs 0 to 20.0 kHz 0.05 +0.05
Stopband attenuation 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 32
Built-in analog LPF compensation 0.4535fs 20.0 kHz 0.34
Frequency band Attenuation (dB)
f @ fs = 44.1 kHz min typ max
Overall frequency characteristic
0
10
20
30
Gain(dB)
40
50
60
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
(× fs)
Passband characteristic
0.0
0.2
0.4
Gain(dB)
0.6
0.8
0.000 0.125 0.250 0.375 0.500
0.4535
(× fs)
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Page 11
SM588× series
2-wire input, deemphasis ON overall characteristics
Parameter
Passband ripple 0 to 0.4535fs 0 to 20.0 kHz 0.09 +0.23
Stopband attenuation 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 36
Built-in analog LPF compensation 0.4535fs 20.0 kHz 0.34
Frequency band Attenuation (dB)
f @ fs = 44.1 kHz min typ max
Deemphasis ON overall frequency characteristic
0
10
20
30
Gain(dB)
40
50
60
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
(× fs)
Deemphasis ON passband characteristic
0
2
4
6
Gain(dB)
8
10
12
0.000 0.125 0.250 0.375 0.500
0.4535
(× fs)
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Page 12
SM588× series
FUNCTIONAL DESCRIPTION
System Clock (CLK)
The system clock CLK frequency varies with device within the series as shown below, where fs is the input
frequency on LRCI.
Note that the input clock accuracy and signal-to-noise ratio greatly inuence the AC analog characteristics. The D/A converter operates at the speed shown in the following table.
Table 1. System clock
Device Master clock
A version 384fs 48fs
B, C version 256/512fs 32fs
DAC oversampling
operation
System Reset
The SM588× series devices incorporate a built-in power-ON reset circuit for system reset.
When power is applied, the internal arithmetic operation and output timing counter are reset, and then reset again and timing synchronized to the external input on the next LRCI rising edge. After system reset, the out­puts are muted until the 9th rising of LRCI when output muting is released.
When the timing is reset, the PWM outputs may generate an output noise. An external muting circuit may be required to prevent this output noise.
VDD
123 910
LRCI
Internal
Reset
LO
RO
Output Muted
Figure 1. System reset timing
NIPPON PRECISION CIRCUITS—12
Page 13
SM588× series
Audio Data Input
Input data format (DATA)
The input data has a format that varies with device within the series, as shown below.
Table 2. Input format
Device Input length Format
SM5882/SM5883
SM5885
1. The 2-wire type supports bit clocks of 48fs (384fs) or 64fs (256fs/512fs) only.
2. The 3-wire type supports bit clocks of up to 64fs.
Input timing
3-wire input (DATA, LRCI, BCKI)
Serial data bits on DATA are read into the SIPO register (serial-to-parallel converter register) on the rising edge of the bit clock BCKI, and then converted to parallel data.
The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset, as long as the clock frequency ratio between LRCI and the system clock CLK is maintained, phase differences between LRCI, BCKI and the system clock CLK do not affect the functional operation. Also, any jitter present on the data input clock does not appear as output pulse jitter.
1
2
16 bits
24 bits
MSB first, bit serial, rear-packed, 2s complement
2-wire input (DATA, LRCI)
Serial data bits on DATA are read into the SIPO register (serial-to-parallel converter register) on the rising edge of an internally generated bit clock, and then converted to parallel data.
Deemphasis Filter (DEEM: 2-wire input)
The 2-wire type with built-in digital deemphasis lter is designed to operate at 44.1 kHz. Deemphasis is ON when DEEM is HIGH, and OFF when DEEM is LOW.
NIPPON PRECISION CIRCUITS—13
Page 14
SM588× series
TIMING DIAGRAMS
2-wire Input Type with Deemphasis Filter Built-in
DATA
Internal bit clock
(Generated by system clock)
LRCI
3-wire Input Type
Left
Channel
MSB LSB
24 bit clock (384fs type)
32 bit clock (256fs/512fs type)
16 or 24 bit
1/fs
LSB
Right
Channel
MSB
16 or 24 bit
24 bit clock (384fs type)
32 bit clock (256fs/512fs type)
DATA
BCKI
(64fs MAX)
LRCI
Left
Channel
1/fs
16 or 24 bit
MSB LSB
Right
Channel
LSB
MSB
16 or 24 bit
NIPPON PRECISION CIRCUITS—14
Page 15
SM588× series
TYPICAL APPLICATIONS
Input Interface Examples (fs = 44.1kHz)
16.9344MHz (384fs)
44.1kHz
3-wire input type
System clock 384fs
11.2896MHz (256fs)
44.1kHz
3-wire input type
System clock 256fs
X'tal
X'tal
LRCI
BCKI
DATA
LRCI
BCKI
DATA
CKI
SM5882/83/85
CKI
SM5882/83/85
16.9344MHz (384fs)
44.1kHz
2-wire input type
System clock 384fs
11.2896MHz (256fs)
44.1kHz
2-wire input type
System clock 256fs
X'tal
X'tal
LRCI
DATA
LRCI
DATA
CKI
SM5882/83/85
CKI
SM5882/83/85
22.5792MHz (512fs)
44.1kHz
3-wire input type
System clock 512fs
X'tal
LRCI
BCKI
DATA
CKI
SM5882/83/85
44.1kHz
2-wire input type
System clock 512fs
X'tal
22.5792MHz (512fs)
LRCI
DATA
CKI
Note that the output analog characteristics and other specifications are not guaranteed for a particular format or application circuit.
SM5882/83/85
NIPPON PRECISION CIRCUITS—15
Page 16
SM588× series
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: +81-3-3642-6661
Facsimile: +81-3-3642-6698
http://www.npc.co.jp/
Email: sales
@npc.co.jp
NIPPON PRECISION CIRCUITS—16
NC9720GE 2000.11
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