Page 1
SM5877AM
NIPPON PRECISION CIRCUITS INC.
3rd-order Σ∆ , 2-channel D/A Converter
OVERVIEW
The SM5877AM is a 3rd-order Σ∆ , 2-channel D/A
converter LSI for digital audio reproduction equipment. It also incorporates an 8-times oversampling
digital filter and analog, post-converter lowpass filters.
The SM5877AM has digital deemphasis filter, attenuator, and soft mute circuits built-in. Double-speed
operation and low-voltage operation are also supported.
The SM5877AM operates from a 2.7 to 5.5 V supply,
and is available in 24-pin SSOPs.
FEATURES
■
2.7 to 5.5 V operating supply voltage range
■
4.5 to 5.5 V operating supply voltage range for
double-speed mode
■
44.1 kHz sampling frequency
■
Normal (384fs) and double-speed (192fs),
16.9344 MHz system clock
■
16.9344 MHz crystal oscillator circuits built-in
■
16-bit, MSB first, rear-packed serial data input
format ( ≤ 64fs bit clock)
■
8-times oversampling digital filter
• 32 dB stopband attenuation
• ± 0.05 dB passband ripple
■
Deemphasis filter operation
• 36 dB stopband attenuation
• − 0.09 to +0.23 dB deviation from ideal deemphasis filter characteristics
■
Attenuator
• 6-bit attenuator (64 steps)
• Soft mute function when MODE is HIGH
(approx. 1024/fs total muting time)
■
Built-in infinity-zero detector
■
Σ∆ 2-channel D/A converter
• 3rd-order noise shaper
• 32fs oversampling (16fs for double-speed
mode)
■
3rd-order analog, post-converter lowpass filters
built-in (165 kHz cut-off frequency)
■
24-pin SSOP
■
Molybdenum-gate CMOS process
PINOUT
1MUTE
2DEEM
3CKO
4DVSS
5BCKI
6DI
SM5877AM
7DVDD
8LRCI
9TSTN
10TO1
11AVDDL
12LO 13 AVSS
PACKAGE DIMENSIONS
Unit: mm
24-pin SSOP
7.80 0.30
5.40 0.20
10.05 0.20
10.20 0.30
0.7 0.8
Package Marking
0.36 0.10
1.80 0.10
2.10MAX
0.10 0.10
24 ATCK
23 MODE
22 RSTN
21 DS
20 XVSS
19 XTO
18 XTI
17 XVDD
16 MUTEO
15 AVDDR
14 RO
0.15
0.50 0.20
MA7785MS
0.1
+
0.05
−
010
NIPPON PRECISION CIRCUITS—1
Page 2
BLOCK DIAGRAM
SM5877AM
LRCI DIBCKI
MODE
ATCK
MUTE
RSTN
DS
DVSS
DVDD
TSTN
TO1
AVDDL
Attenuation
counter
Timing
control
PWM data
generation block
Filter & attenuation
L
R
Input interface
LR
operation block
LR
Noise shaper
operation block
MUTEO
DEEM
CKO
XVSS
XTO
XTI
XVDD
AVDDR
+−
LO AVSS RO
+−
PIN DESCRIPTION
Number Name I/O Description
1 MUTE Ip
2 DEEM Ip Deemphasis control. Deemphasis is ON when HIGH, and OFF when LOW.
3 CKO O 16.9344 MHz clock output
4 DVSS Digital ground pin
5 BCKI Ip Bit clock input pin
6 DI Ip Serial data input pin
7 DVDD Digital supply pin
8 LRCI Ip
9 TSTN Ip Test pin. Test mode when LOW.
When MODE is HIGH: Soft mute ON/OFF control. Mute is active when HIGH.
When MODE is LOW: Attenuator level direction control. The attenuator direction is
down when HIGH.
Input sample data rate (fs) clock input pin. Left-channel input when HIGH, and rightchannel input when LOW.
NIPPON PRECISION CIRCUITS—2
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−
−
+
−
+
−
°
°
−
−
−
−
−
−
±
−
° C
SM5877AM
Number Name I/O Description
10 TO1 O Test output 1. Normally LOW.
11 AVDDL Left-channel analog supply pin
12 LO O Left-channel analog output
13 AVSS Analog ground pin
14 RO O Right-channel analog output
15 AVDDR Right-channel analog supply pin
16 MUTEO O Infinity-zero detection output
17 XVDD Crystal oscillator supply pin
18 XTI I Crystal oscillator or 16.9344 MHz external clock input pin
19 XTO O Crystal oscillator output pin
20 XVSS Crystal oscillator ground pin
21 DS Ip Double/Normal-speed mode select. Double-speed mode when HIGH.
22 RSTN Ip Reset pin. Reset when LOW.
23 MODE Ip Soft mute/attenuator mode select. Soft mute mode when HIGH.
24 ATCK Ip Attenuator level setting clock. Disabled when MODE is HIGH.
SPECIFICATIONS
Absolute Maximum Ratings
DV
= AV
SS
Supply voltage range DV
Input voltage range
XTI input voltage range V
Storage temperature range T
Power dissipation P
Soldering temperature T
Soldering time t
1. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK.
Also applicable during supply switching.
Recommended Operating Conditions
Normal-voltage: DV
Supply voltage range DV
Supply voltage variation
Operating temperature range T
SS
= XV
= 0 V, AV
SS
DD
= AV
DDL
= AV
DDR
Parameter Symbol Rating Unit
, AV
DD
1
SS
= AV
SS
= XV
= 0 V, AV
SS
DD
V
= AV
Parameter Symbol Rating Unit
, AV
DD
DV
DD
DV
DD
XV
DD
DV
SS
DV
SS
XV
SS
sld
IN1
IN
stg
sld
opr
DD
D
DD
XV
AV
AV
XV
AV
AV
, XV
DDL
, XV
DD
DD
DD
SS
SS
SS
DD
= AV
DD
,
,
,
,
,
DDR
0.3 to 7.0 V
DV
0.3 to DV
XV
SS
SS
0.3 to XV
DD
DD
40 to 125
250 mW
255
10 s
4.5 to 5.5 V
0.1 V
40 to 85
0.3 V
0.3 V
C
C
NIPPON PRECISION CIRCUITS—3
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SM5877AM
−
−
−
−
Low-voltage: DV
SS
= AV
SS
= XV
= 0 V, AV
SS
DD
= AV
Parameter Symbol Rating Unit
Supply voltage range DV
Supply voltage variation
, AV
DD
DV
DD
DV
DD
XV
DD
DV
SS
DV
SS
XVSS − AV
Operating temperature range T
DC Electrical Characteristics
Normal-voltage: DV
AV
, T
DDR
DVDD digital supply current
XVDD system clock supply
current
AVDD analog supply current
XTI HIGH-level input voltage V
XTI LOW-level input voltage V
XTI AC-coupled input voltage V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CKO HIGH-level output voltage V
CKO LOW-level output voltage V
XTI HIGH-level input current I
XTI LOW-level input current I
LOW-level input current
Input leakage current
1. DV
2. I
DDA
3. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK.
4. Pins TO1 and MUTEO.
= − 40 to 85 ° C
a
Parameter Symbol Condition
1
= AV
DD
= XV
DD
is the total current.
= AV
SS
3
3
4
4
4
4
= 5 V, DS = 5 V (double speed), XTI clock input frequency f
DD
= XV
SS
1
1
I
DDD
I
DDX
I
DDA
V
V
V
V
I
IH1
IL1
INAC
IH2
IL2
OHA
OLA
OHC
OLC
IH1
IL1
IL2
I
LH
= 0 V, DV
SS
2
DD
Clock input 0.7XV
Clock input – – 0.3XV
IOH = −1 mA
IOL = 1 mA – – 0.4 V
IOH = −1 mA
IOL = 1 mA – – 0.4 V
VIN = XV
DD
VIN = 0 V – 12 25 µA
VIN = 0 V – 12 25 µA
VIN = DV
DD
DDL
, XV
DD
XV
AV
AV
XV
− AV
opr
= AV
= AV
DDR
DD
,
DD
,
DD
,
DD
,
SS
,
SS
SS
DD
= XV
= 4.5 to 5.5 V, AV
DD
min typ max
–1525mA
–25mA
–48mA
DD
0.3XV
DD
2.4 – – V
– – 0.5 V
−
AV
DD
0.4
−
DV
DD
0.4
–1225µA
– – 1.0 µA
= 16.9344 MHz, no output load.
XTI
2.7 to 4.5 V
±0.1 V
−20 to 70 °C
= AV
DD
DDL
Rating
Unit
––V
DD
––V
V
p-p
––V
––V
=
NIPPON PRECISION CIRCUITS—4
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SM5877AM
Low-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AV
Ta = −20 to 70 °C
DD
DD
−
−
Rating
––V
––V
––V
––V
Parameter Symbol Condition
DVDD digital supply current
XVDD system clock supply
1
current
AVDD analog supply current
XTI HIGH-level input voltage V
XTI LOW-level input voltage V
XTI AC-coupled input voltage V
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CKO HIGH-level output voltage V
CKO LOW-level output voltage V
XTI HIGH-level input current I
XTI LOW-level input current I
LOW-level input current
Input leakage current
1
1
3
3
4
4
4
4
I
DDD
I
DDX
I
DDA
V
V
V
V
I
IH1
IL1
INAC
IH2
IL2
OHA
OLA
OHC
OLC
IH1
IL1
IL2
I
LH
2
Clock input 0.7XV
Clock input – – 0.3XV
IOH = −0.5 mA
IOL = 0.5 mA – – 0.4 V
IOH = −0.5 mA
IOL = 0.5 mA – – 0.4 V
VIN = XV
DD
VIN = 0 V – 4 15 µA
VIN = 0 V – 4 15 µA
VIN = DV
DD
1. DVDD = AVDD = XVDD = 3 V, DS = 0 V (normal speed), XTI clock input frequency f
2. I
is the total current.
DDA
3. Pins MUTE, DEEM, BCKI, DI, LRCI, TSTN, DS, RSTN, MODE and ATCK.
4. Pins TO1 and MUTEO.
min typ max
–69mA
–13mA
–12mA
0.3XV
2.4 – – V
– – 0.5 V
AV
DD
0.4
DV
DD
0.4
–415µA
– – 1.0 µA
= 16.9344 MHz, no output load.
XTI
DDL
DD
= AV
Unit
V
p-p
DDR
,
AC Electrical Characteristics
Normal-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 4.5 to 5.5 V, AVDD = AV
AV
, Ta = −40 to 85 °C
DDR
Low-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 2.7 to 4.5 V, AVDD = AV
Ta = −20 to 70 °C
System clock (XTI)
Crystal Oscillator
Parameter Symbol
Oscillator frequency f
OSC
min typ max
4.0 16.9344 17.8 MHz
Rating
DDL
= AV
DDL
Unit
DDR
=
,
NIPPON PRECISION CIRCUITS—5
Page 6
External clock input
SM5877AM
Parameter Symbol
HIGH-level clock pulsewidth t
LOW-level clock pulsewidth t
Clock pulse cycle t
XTI input clock
t
CWH
t
XI
Serial input (BCKI, DI, LRCI)
Parameter Symbol
BCKI HIGH-level pulsewidth t
BCKI LOW-level pulsewidth t
BCKI pulse cycle t
DI setup time t
DI hold time t
Last BCKI rising edge to LRCI edge t
LRCI edge to first BCKI rising edge t
CWH
CWL
XI
BCWH
BCWL
BCY
DS
DH
BL
LB
t
CWL
Rating
Unit
min typ max
26.0 29.5 125 ns
26.0 29.5 125 ns
56.0 59.0 250 ns
Rating
Unit
min typ max
50 – – ns
50 – – ns
6t
XI
––ns
50 – – ns
50 – – ns
50 – – ns
50 – – ns
0.5V
V
IH1
DD
V
IL1
Serial input timing
BCKI
DI
LRCI
t
BCY
t
BCWH
t
DS
t
DH
t
BL
t
BCWL
1.5 V
1.5 V
t
LB
1.5 V
NIPPON PRECISION CIRCUITS—6
Page 7
SM5877AM
Control input (MUTE, MODE, ATCK, DEEM, DS)
Parameter Symbol
ATCK LOW-level pulsewidth t
ATCK HIGH-level pulsewidth t
MUTE setup time t
MUTE hold time t
MODE setup time t
MODE hold time t
Rise time t
Fall time t
Control input timing
MUTE
MODE
ATCK
t
t
MUS
MOS
t
MUH
t
MOH
ATWL
ATWH
MUS
MUH
MOS
MOH
r
f
Rating
Unit
min typ max
0.5/fs – – µs
0.5/fs – – µs
100 – – ns
100 – – ns
100 – – ns
100 – – ns
– – 50 ns
– – 50 ns
1.5 V
1.5 V
t
ATWL
DEEM
DS
MUTE
MODE
ATCK
Reset Input (RSTN)
Parameter Symbol
RSTN LOW-level pulsewidth after supply rising
edge
2.4 V
t
ATWH
0.5 V
t
f
t
RSTN
t
r
2.4 V
0.5 V
Rating
min typ max
50 – – ns
1.5 V
Unit
NIPPON PRECISION CIRCUITS—7
Page 8
Theoretical Filter Characteristics
Deemphasis OFF overall characteristics
SM5877AM
Parameter
Frequency band Attenuation (dB)
f @ fs = 44.1 kHz min typ max
Passband ripple 0 to 0.4535fs 0 to 20.0 kHz −0.05 – +0.05
Stopband attenuation
Built-in analog LPF
compensation
0.5465fs to
7.4535fs
24.1 to 328.7 kHz 32 – –
0.4535fs 20.0 kHz – −0.34 –
Overall frequency characteristic (deemphasis OFF)
0
10
20
30
Gain (dB)
40
50
60
0.0
Passband characteristic (deemphasis OFF)
0.0
0.2
0.4
Gain (dB)
0.6
0.8
Frequency (fs)
Frequency (fs)
8.07.06.05.04.03.02.01.0
0.5000.3750.2500.125 0.45350.000
NIPPON PRECISION CIRCUITS—8
Page 9
Deemphasis ON overall characteristics
SM5877AM
Parameter
Frequency band Attenuation (dB)
f @ fs = 44.1 kHz min typ max
Deviation from ideal
deemphasis filter characteristics
0 to 0.4535fs 0 to 20.0 kHz −0.09 – +0.23
Stopband attenuation 0.5465fs to 7.4535fs 24.1 to 328.7 kHz 36 – –
Built-in analog LPF
compensation
0.4535fs 20.0 kHz – −0.34 –
Overall frequency characteristic (deemphasis ON)
0
10
20
30
Gain (dB)
40
50
60
0.0
Passband characteristic (deemphasis ON)
0
2
4
6
Gain (dB)
8
10
12
0.000
Frequency (fs)
Frequency (fs)
8.07.06.05.04.03.02.01.0
0.5000.3750.2500.125 0.4535
NIPPON PRECISION CIRCUITS—9
Page 10
AC Analog Characteristics
SM5877AM
Normal-voltage: DVSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 5 V, AVDD = AV
0 V, DEEM = 0 V, crystal oscillator frequency f
Parameter Symbol Condition
Total harmonic distortion THD + N 1 kHz, 0 dB – 0.004 0.010 %
LSI output level V
Evaluation board output level V
Dynamic range D.R 1 kHz, −60 dB 91 97 – dB
Signal-to-noise ratio
Channel separation Ch. Sep 1 kHz, −∞/0 dB 87 93 – dB
1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper
noise.
1
out1
out2
S/N 1 kHz, 0/−∞ dB 90 96 – dB
Low-voltage: D VSS = AVSS = XVSS = 0 V, DVDD = AVDD = XVDD = 3 V, AVDD = AV
DEEM = 0 V, crystal oscillator frequency f
Parameter Symbol Condition
Total harmonic distortion THD + N 1 kHz, 0 dB – 0.009 0.030 %
LSI output level V
Evaluation board output level V
Dynamic range D.R 1 kHz, −60 dB 74 86 – dB
Signal-to-noise ratio
Channel separation Ch. Sep 1 kHz, −∞/0 dB 72 82 – dB
1
S/N 1 kHz, 0/−∞ dB 74 84 – dB
OSC
out1
out2
= 16.9344 MHz, Ta = 25 °C
OSC
Rating
min typ max
1 kHz, 0 dB 1.1 1.2 1.3 V
1 kHz, 0 dB – 1.2 – V
DDL
= 16.9344 MHz, Ta = 25 °C
Rating
min typ max
1 kHz, 0 dB 0.65 0.71 0.77 V
1 kHz, 0 dB – 0.71 – V
DDL
= AV
= AV
DDR
, DS =
DDR
Unit
rms
rms
, DS = 0 V,
Unit
rms
rms
1. Signal-to-noise is measured following a device reset, with DATA = 0 (DI = LOW). Under these conditions, the signal-to-noise ratio includes noise-shaper
noise.
NIPPON PRECISION CIRCUITS—10
Page 11
SM5877AM
AC Measurement Circuit and Conditions
Measurement circuit block diagram
CKO (384fs)
Left channel
Right channel
Signal
generator
BCK
LRCK (fs)
DATA
Evaluation
board
Left/Right
channel selector
Distortion
analyzer
fs = 44.1 kHz
DATA = 16 bits
NF Corporation 3346A.
10 kΩ input impedance
Measurement conditions
Parameter
1
Symbol
Total harmonic distortion THD + N
Output level V
out
Dynamic range DR D-RANGE
Signal-to-noise ratio S/N THRU
Channel separation Ch. Sep THRU
1. Pins LO and RO should have an output load of 10 kΩ (min).
3346A left/right-channel
selector switch
THRU
Shibasoku AD725C.
RMS measurement
AD725C distortion analyzer
with built-in filter
20 kHz lowpass filter ON
400 Hz highpass filter OFF
20 kHz lowpass filter ON
400 Hz highpass filter OFF
JIS A filter ON
20 kHz lowpass filter ON
400 Hz highpass filter OFF
NIPPON PRECISION CIRCUITS—11
Page 12
Measurement circuit
SM5877AM
100p
5.6k
R
VCC
OUTPUT
VEE
100p
100
L
OUTPUT
100p
100
+
10u0.1u
100k
2.2u
+
U2 1/2
220p
NJM2100D
+
-
6.8k
0.1u 10u
5.6k
220p
1500p
5.6k
22k
22k
U2
33k
-
1/2
NJM2100D
+
100p
22k
33k
-
+
33u
22k
22k
+
33k
22k
33u
100k
2.2u
U3 1/2
NJM2100D
+
-
6.8k
1500p
5.6k
22k
+
33u
U3
1/2
NJM2100D
+
22k
+
33k10u
33u
10u
AVSSAVDD
+
100u
100u+0.01u
1000p
680
LO AVSS
12 13
RO
X’tal
14
AVDDR
15
MUTEO
16
XVDD
17
18
XTI
XTO
19
XVSS
20
DS
21
RSTN
22
MODE
23
ATCK
24
0.01u
10p10p
SW1
AVDDL
11
TO1
10
9
TSTN
LRCI
8
DVDD
7
DI
6
BCKI
5
DVSS
4
CKO
3
DEEM
2
SM5877AM
MUTE
1
680
0.01u+100u
1000p
DVDD
DVSS
+
100u0.1u
SW3 SW4
SW2
DS
CKO
MODE
ATCK
LRCI
BCKI
RSTN
DEEM
MUTE
DI
NIPPON PRECISION CIRCUITS—12
Page 13
SM5877AM
FUNCTIONAL DESCRIPTION
System Clock/Speed Switching (XTI, XTO, CKO, DS)
The system clock on XTI can be set to run at one of
two speeds, 384fs (normal speed) or 192fs (doublespeed), where fs is the input frequency on LRCI. The
speed for CD playback is set by the input level on
DS, as shown in table 1. The system clock should be
fixed at 16.9344 MHz.
Table 1. System clock select
DS
Parameter Symbol
LOW
(normal
speed)
HIGH
(double
speed)
Note that the input clock accuracy and signal-tonoise ratio greatly influence the AC analog characteristics. Accordingly, care should be taken to ensure
that the clock is free from jitter.
The system clock can be controlled by a crystal
oscillator comprising a crystal connected between
XTI and XTO and the built-in CMOS inverter. Alternatively, an external system clock can be input on
XTI. As the internal CMOS inverter has a feedback
resistor, the external clock can be AC coupled to
XTI. The system clock is output on CKO.
XTI input clock
frequency
CD playback
XTI frequency
CKO output
clock frequency
Internal system
clock period
f
XI
(= 1/tXI)
f
XI
f
CO
T
SYS
384fs 192fs
16.9344 MHz
at fs = 44.1
kHz
384fs 192fs
t
XI
16.9344 MHz
at fs = 88.2
kHz
t
XI
System Reset (RSTN)
The device should be reset in the following cases.
■ At power ON
■ When LRCI and/or the system clock XTI stop, or
other abnormalities occur.
RSTN
LRCI
LOW
123 910
The device is reset by applying a LOW-level pulse on
RSTN. At system reset, the internal arithmetic operation and output timing counter are synchronized on
the next LRCI rising edge, as shown in figure 1.
Internal reset
LO
RO
Figure 1. System reset timing
Audio Data Input (DI, BCKI, LRCI)
The digital audio data is input on DI in MSB-first, 2scomplement, 16-bit serial format.
Serial data bits are read into the SIPO register (serialto-parallel converter register) on the rising edge of the
bit clock BCKI.
The arithmetic operation and output timing are independent of the input timing. Accordingly, after a reset,
Outputs muted
as long as the clock frequency ratio between LRCI
and the system clock XTI is maintained, phase differences between LRCI, BCKI and the system clock
XTI do not affect the functional operation. Also, any
jitter present on the data input clock does not appear
as output pulse jitter.
The bit clock frequency on BCKI should be between
32fs and 64fs.
NIPPON PRECISION CIRCUITS—13
Page 14
SM5877AM
Deemphasis Filter (DEEM)
The built-in digital deemphasis filter is designed to
operate at 44.1 kHz. Deemphasis is ON when DEEM
is HIGH, and OFF when DEEM is LOW.
Attenuation (MDT, MCK, MLEN)
The digital attenuation mode is selected when
MODE is LOW. The attenuator operates by multi-
The gain is set by the counter contents DATT as fol-
lows.
plying the internal 6-bit up/down counter’s output
data with the signal data.
The direction of the 6-bit up/down counter is con-
Gain 20
DATT
--------------- -
log× [dB]=
63
trolled by the level on MUTE (down when MUTE is
HIGH, and up when MUTE is LOW). The count is
advanced on the rising edge of ATCK.
When the count reaches 0 (down) or 63 (up), the
Upon system initialization or when MODE changes
state, DATT is set to 63, which corresponds to the
maximum gain of 0 dB as shown in table 2.
counter automatically stops.
Table 2. Attenuator gain
DATT Gain (dB) DATT Gain (dB) DATT Gain (dB) DATT Gain (dB)
63 0.0 47 −2.545 31 −6.160 15 −12.465
62 −0.139 46 −2.732 30 −6.444 14 −13.064
61 −0.280 45 −2.923 29 −6.739 13 −13.708
60 −0.424 44 −3.118 28 −7.044 12 −14.403
59 −0.570 43 −3.317 27 −7.360 11 −15.159
58 −0.718 42 −3.522 26 −7.687 10 −15.987
57 −0.869 41 −3.731 25 −8.028 9 −16.902
56 −1.023 40 −3.946 24 −8.383 8 −17.925
55 −1.180 39 −4.166 23 −8.752 7 −19.085
54 −1.339 38 −4.391 22 −9.138 6 −20.424
53 −1.501 37 −4.623 21 −9.542 5 −22.007
52 −1.667 36 −4.861 20 −9.966 4 −23.946
51 −1.835 35 −5.105 19 −10.412 3 −26.444
50 −2.007 34 −5.357 18 −10.881 2 −29.966
49 −2.183 33 −5.617 17 −11.378 1 −35.987
48 −2.362 32 −5.884 16 −11.904 0 −∞
Soft Mute (SMUTE)
Soft mute mode is selected when MODE is HIGH.
The up/down counter is switched to internal clock
drive, and soft mute operation is controlled by
MUTE only.
When MUTE goes HIGH, the up/down counter
counts down. The total time to go from 0 to maximum mute is 1024/fs. This corresponds to approximately 23.2 ms at fs = 44.1 kHz.
When MUTE is LOW, soft mute is released. The
attenuation counter output counts up, increasing the
gain. The time taken to return to 0 dB is also 1024/fs.
Soft mute operation is shown in figure 2.
Upon system initialization or when MODE changes
state, mute is released, which corresponds to the
maximum gain of 0 dB.
NIPPON PRECISION CIRCUITS—14
Page 15
SM5877AM
Infinity-Zero (MUTEO)
MUTE
0 dB
Gain
– ∞
1024/fs 1024/fs
Figure 2. Soft mute operation example
1 2 3 8 9
LRCI
DI
RSTN
MUTEO
Initialize
TIMING DIAGRAMS
Input Timing (DI, BCKI, LRCI)
The SM5877AM outputs an infinity-zero detection
output signal under the following circumstances.
■ From immediately after a reset input on RSTN
until the initialization cycle finishes and the first
data cycle occurs.
■ When an infinity-zero occurs in the input data.
When an infinity-zero is detected, a period of 2
× (1/fs) ≈ 0.37 seconds takes place before
MUTEO goes HIGH.
14
2 /fs
Signal SignalNo Signal
Figure 3. MUTEO output timing
14
MSB LSB MSB LSB
Left channel Right channel
DI
BCKI
(64fs max)
LRCI
TYPICAL APPLICATIONS
Input Interface Circuits
Normal Speed
Sony
CXD2500
PSSL
1/fs
16 bits 16 bits
16.9344 MHz crystal
XTAI
LRCK
DA16
DA15
16.9344 MHz
44.1 kHz
2.1168 MHz
XTI XTO
CKO
LRCI
DI
BCKI
SM5877
DS
NIPPON PRECISION CIRCUITS—15
Page 16
SM5877AM
16.9344 MHz crystal
Double Speed
SEL
PSSL
Matsushita
MN6617
IPSEL
Sony
CXD2500
Normal/double
speed control
R/L
SRDATA
SRCK
XTAI
LRCK
DA16
DA15
X1
16.9344 MHz
44.1 kHz
2.1168 MHz
16.9344 MHz
44.1 kHz (88.2 kHz)
2.1168 MHz (4.2336 MHz)
( ) indicate double-speed mode
XTI XTO
CKO
LRCI
DI
BCKI
CKO
LRCI
DI
BCKI
DS
Normal Double speed
SM5877
DS
16.9344 MHz crystal
XTI XTO
SM5877
Note that the output analog characteristics and other
specifications are not guaranteed for a particular format or application circuit. Pins LO and RO should
have an output load of 10 kΩ (min).
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
NIPPON PRECISION CIRCUITS INC.
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9501AE 1995.06
NIPPON PRECISION CIRCUITS—16
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