Datasheet SM5165AV Datasheet (NPC)

−

SM5165AV

NIPPON PRECISION CIRCUITS INC.

OVERVIEW

The SM5165AV is a PLL synthesizer IC developed
for application in pagers and fabricated using NPC’s
Molybdenum-gate CMOS process. It incorporates
independently-controlled reference frequency and
operating frequency dividers, and operates from a
low-voltage supply to realize low power dissipation.

FEATURES

■

Up to 90 MHz operating frequency
(V

= V

DD1

■

Up to 100 MHz operating frequency
(V

= V

DD1

■

Supply voltages

•V

DD1

(prescaler, counters)

•V

DD3

■

40 to 16376 reference frequency divider ratio
range (with 1/8 prescaler built-in)

■

1056 to 262143 operating frequency divider ratio
range

■

Power-save function for reduced power
dissipation

■

10 to 60 ° C operating temperature range

■

16-pin VSOP

■

Molybdenum-gate CMOS process

= 0.95 V)

DD2

= 1.00 V)

DD2

= V

= 0.95 to 1.5 V

DD2

= 2.0 to 3.3 V (charge pump)

PLL Synthesizer IC

PINOUT

PACKAGE DIMENSIONS

Unit: mm

16-pin VSOP

(TOP VIEW)

VDD1

FIN
VSS

RO

TEST

DO

DB
NC

16pin VSOP

1

8

4.4 0.2

6.4 0.2

5165
AV

16

XIN
XOUT
LE
CLK
DATA
OPR
VDD2

9

VDD3

APPLICATIONS

■

Pagers

ORDERING INFOMATION

Device Package

SM5165AV 16pin VSOP

0.22

5.1 0.2

+ 0.10

- 0.05

+ 0.10

- 0.05

0.15

010

0.65

1.15 0.1

0.10 0.05

NIPPON PRECISION CIRCUITS—1

0.5 0.2

∗

BLOCK DIAGRAM

SM5165AV

XIN

XOUT

VDD2

VDD2

AREA

DATA

CLK

SELECTER

LE

∗

OPR

VDD1

FIN

PIN DESCRIPTION

1/8

PRESCALER

VDD1

11 BIT

R COUNTER

AREA

11 BIT LATCH

LATCH

22 BIT

SHIFT REGISTER

18 BIT LATCH

VDD1

AREA

Protection diodes are connected to VDD3. Logic level : V

18 BIT

N COUNTER

LEVEL

SHIFTER

PHASE

DETECTOR

LEVEL

SHIFTER

GENERATOR

VDD2

AREA

SHIFTER

WINDOW

to V

DD2

DD3

LEVEL

VDD3

AREA

BOOSTER

S. G.

CHARGE

PUMP

TEST
RO

VDD3

DB

DO

VDD2

AREA

VSS

Number Name I/O Description

1 VDD1 – Reference frequency and comparator frequency prescaler and counter 1 V supply

2 FIN I

3 VSS1 – Ground pin

4ROO

5 TEST I

6DOO

7 DB O Booster signal output for faster locking
8 NC – No connection
9 VDD3 – Phase comparator, charge pump and booster signal 3 V supply

10 VDD2 –

11 OPR I

12 DATA I Control data input pin
13 CLK I Control data clock input pin
14 LE I Control data latch enable signal input pin
15 XOUT O Reference frequency divider crystal oscillator connection pins. Alternatively, an external clock input can

16 XIN I

Operating frequency divider input pin.
Feedback resistor b uilt-in f or AC-coupled inputs.

Test output.
LOW-level output for (1, 0) test bit patter. Leave open for normal operation.

Test pin.
Pull-down resistor built-in. Leave open or connect to ground for normal operation.

Phase detector output pin.
Built-in charge pump and tristate output means that this output can be connected to a low-pass filter.
The output polarity is preset for connection to a passive filter.

Shift register and latch 1 V supply.
Should be kept at the same potential as VDD1.

Power-save control pin.
Operation when HIGH, standby mode when LOW.

be connected to XIN. The clock is also output on XOUT.
Feedback resistor b uilt-in f or AC-coupled inputs.

NIPPON PRECISION CIRCUITS—2

SPECIFICATIONS

Absolute Maximum Ratings

V

= 0 V

SS

Parameter Symbol Condition Rating Unit

Supply voltage

Input voltage range

Storage temperature range T
Power dissipation P
Soldering temperature T
Soldering time t

V

V

V
V

DD1,2

DD3

IN1

IN2

stg

D

sld

sld

−

−

−

−

−

°

°

−

° C

SM5165AV

0.3 to 2.0 V

0.3 to 7.0 V
FIN, XIN, TEST V
OPR, CLK, DATA, LE V

SS

SS

0.3 to V

0.3 to V

+ 0.3 V

DD1,2

+ 0.3 V

DD3

40 to 125

150 mW
255

10 s

C

C

Recommended Operating Conditions

V

= 0 V

SS

Parameter Symbol Condition Rating Unit

V

Supply voltage

Storage temperature range T

DD1,2

V

DD3

stg

Electrical Characteristics

V

= 0 V, V

SS

VDD1, VDD2 operating current
consumption

VDD3 operating current consumption I
VDD2 standby current I
VDD3 standby current I

FIN maximum operating input frequency f

XIN maximum operating input frequency f
FIN minimum operating input frequency f
XIN minimum operating input frequency f

FIN input amplitude V

XIN input amplitude V
OPR, CLK, DATA, LE LOW-level input

voltage

DD1

= V

= 0.95 to 1.5 V, V

DD2

DD3

Parameter Symbol Condition

Note 1. – 0.70 1.10

I

DD1

Note 2. – 0.75 1.20

DD2

DD3

Note 3.

DD4

max1

max2

300 mVp-p sine
wave

300 mVp-p sine wave. Note 4. 16 – – MHz
300 mVp-p sine wave – – 40 MHz

min1

300 mVp-p sine wave. Note 4. – – 9 M Hz

min2

V

DD1,2

AC coupling

FIN

V

DD1,2

AC coupling
f

XIN

V

IL

= 16 MHz, AC coupling 0.3 – – Vp-p

XIN

= 2.0 to 3.3 V, T

V

DD1,2

1.50 V
V

DD1,2

1.50 V

= 0.95 to 1.50 V, f

= 1.00 to 1.50 V, f

FIN

FIN

= − 10 to 60 ° C

a

= 0.95 to

= 1.00 to

= 90 MHz,

= 100 MHz,

0.95 to 1.5 V

2.0 to 3.3 V
10 to 60

Rating

Unit

min typ max

mA

–10–µA
– 0.1 – µA
– 0.01 10.0 µA

90 – –

MHz

100 – –

0.3 – –
Vp-p

0.3 – –

– – 0.2V

DD2

V

NIPPON PRECISION CIRCUITS—3

SM5165AV

−

Parameter Symbol Condition

OPR, CLK, DATA, LE HIGH-level input
voltage

FIN LOW-level input current I
XIN LOW-level input current I
FIN HIGH-level input current I
XIN HIGH-level input current I
DO , DB LOW-level output current I
DO, DB HIGH-level output current I

Tristate output high-impedance leakage
current

DATA → CLK setup time t
CLK → LE setup time t
Hold time t

1. V

= V

DD1

output load

2. V

DD1

output load

3. V

DD1

4. Externally-input sine wave

= 0.95 to 1.05 V, V

DD2

= V

= 1.00 to 1.05 V, V

DD2

= 0 V , V

DD2

= 0.95 to 1.05 V, V

= 2.7 to 3.3 V, f

DD3

= 2.7 to 3.3 V , f

DD3

= 2.7 to 3.3 V , OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V)

DD3

5. DO and DB outputs are derived from the V

6. DO and DB outputs are derived from the V

7. Setup and hold times.

I

DD3
DD3

V

IH

IL1

V

= 0 V

IL2

IH1

IH2

OL

OH

I

OZL

OZH

SU1

SU2

H

supply. V
supply. V

IL

V

= V

IH

DD1

Note 5. 1.0 – – mA
Note 6. 1.0 – – mA
V

= 0 V – – 100 nA

OL

V

= V

OH

DD3

Note 7.

= 90 MHz (300 mVp-p sine wave), f

FIN

= 100 MHz (300 mVp-p sine wave), f

FIN

= 2.7 to 3.3 V , V

DD3

= 2.7 to 3.3 V , V

DD3

OL
OH

= 0.4 V

= V

DD3

Rating

min typ max

0.8V

DD2

–V

DD3

––60µA
––10µA
––60µA
––10µA

– – 100 nA
2––µs
2––µs
2––µs

= 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no

XIN

= 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no

XIN

0.4 V

Unit

V

DATA

CLK

LE

VIH

tSU1

VIH

tH

VIH

tSU2

VIH

NIPPON PRECISION CIRCUITS—4

FUNCTIONAL DESCRIPTION

SM5165AV

Operating Frequency Divider
(N-counter) Structure

The operating frequency divider generates a compar­ator frequency signal (FV), which is input to the
phase comparator, by dividing the VCO signal input
on pin FIN.

The operating frequency divider is comprised by
dual modulus prescalers, a 5-bit swallow counter and
a 13-bit main counter.

The settings for the dual modulus prescaler (P and P
+ 1), swallow counter (S) and main counter (M) are
related to the comparator frequency divider ratio by:

NP1+()SPMS–()+×=

PM S+=

The counter value ranges are P = 32, P + 1 = 33, S =
0 to 31, and M = 32 to 8191. Therefore, the compara­tor frequency divider ratio range N is 1056 to

262143.

Reference Frequency Divider
(R-counter) Structure

The reference frequency divider generates a compar­ator frequency signal (FR), which is input to the
phase comparator, by dividing the reference oscilla­tor frequency input either from an external signal on
XIN or from a crystal oscillator connected between
XIN and XOUT.

The reference frequency divider is comprised by a
fixed divide-by-8 prescaler and an 11-bit reference
counter.

The settings for the prescaler (A = 8) and reference
counter (R) are related to the reference frequency
divider ratio by:

RAB8B==
The counter value ranges are A = 8 and B = 5 to

2047. Therefore, the reference frequency divider
ratio range is R = 40 to 16376.

Input Data

The input data should be specified keeping in mind
both the V
using CLK, DATA and LE pins into the shift register
and latch which operate from the V
ever, the input voltages can be specified using either
the V

DD2

The control data input uses a 3-line 23-bit serial
interface comprising the clock (CLK), data input
(DATA) and latch enable (LE). The data is input with
the MSB first. The last (23rd) bit is used as the latch
select control bit. Data is written to the shift register
on the rising edge of the clock signal. Accordingly,
the data should change state on the falling edge of
the clock signal. Data is transferred from the shift
register to the latch when the latch enable (LE) sig­nal goes HIGH. Accordingly, the latch enable signal
should be held LOW while data is being written to
the shift register.

The clock and data input signals are both ignored
when the latch enable signal goes HIGH.

DD2

or V

and V

DD3

supply levels.

DD3

supplies. The data is input

supply. How-

DD2

Input data format

CLK

CLK

1234567891011121314151617

DATA

DATA

1234567891011121314151617

MSB

MSB

LE

LE

18 19 20 21 22 23

18 19 20 21 22 23

NIPPON PRECISION CIRCUITS—5

LSB

LSB

CONTROL

CONTROL

SM5165AV

Latch select

The last (23rd) data bit determines the shift register data latch.

Bit 23 Latch

Reference frequency counter divider ratio data latch

0

select
Swallow counter and main counter frequency divider

1

ratio and DO output latch select

Swallow counter, main counter frequency divider data and DO output

MSB

DATA

1234567891011121314151617

1211109876543210432

2222222222222222

Main counter

(13-bit : 32 to 8191)

Latch select bit. Setting "1"

Swallow counter

(5-bit : 0 to 31)

DO output select bits

18 19 20 21 22 23

10

22

No

meaning

Bits 19 and 20 have no meaning. These bits should be set to 0.
Bits 20 and 21 control the state of the DO output pin.

Bit 21 Bit 22 DO output

00
10
01
11

The DO output polarity can be set by master-slice for either a passive or active filter.

High impedance

Normal operation

Input data example

If the VCO output is (f

) trebled, the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH:

VCO

comparator frequency (fR) × 3) is 25 kHz, then the comparator frequency divider ratio N is given by:

LSB

f

N

--------- ­f

LO
CH

f

VCO

----------------------­fR3×

3×

251.3 3⁄

-------------------- 10052 32 314 4+×== = = =

0.025 3⁄

Therefore, the swallow counter count is 4 (00100)2 and the main counter count is 314 (0000100111010)2.

Input

Data

MSB

1234567891011121314151617

1211109876543210432

2222222222222222

00001001110100010000111

Main counter

(13-bit : 32 to 8191)

Latch select bit. Setting "1"

Swallow counter

(5-bit : 0 to 31)

DO output select bits

18 19 20 21 22 23

10

22

No

meaning

NIPPON PRECISION CIRCUITS—6

LSB

SM5165AV

Reference counter frequency divider setting

DATA

MSB

1234567891011121314151617

No meaning

Test bits

109876543 210

22222222222

Reference counter

(11-bit : 5 to 8191)

18 19 20 21 22 23

meaning

LSB

No

Latch select bit. Set "0"

Bits 1 to 7 and bits 21 and 22 have no meaning. These bits should be set to 0.
Bits 8 and 9 are used for testing at the manufacturers and should be set to 1 and 0, respectively, for normal

operation.

Input data example

If the VCO output is (f

) trebled, the crystal oscillator frequency is 12.8 MHz and the channel bandwidth

VCO

(fCH: comparator frequency (fR) × 3) is 25 kHz, then the reference frequency divider ratio R is given by:

NR

Xtal

---------- ­f

CH

Xtal

--------------­fR3×

12.8

-------------------- 1536 8 192×== = ==

0.025 3⁄

Therefore, the reference counter count is 192 (00011000000)2.

Input

Data

MSB

1234567891011121314151617

00000001000011000000000

109876543 210

22222222222

No meaning

Test bits

Reference counter

(11-bit : 5 to 8191)

18 19 20 21 22 23

meaning

LSB

No

Latch select bit. Set "0"

Boost-up Signal

When the PLL starts up with some phase tolerance, a
level signal is output on pin DB. When the PLL
phase error comes within the tolerance before in
lock, output DB goes high impedance.

When the PLL starts up, the signal on DB charges
the low-pass filter capacitor in anticipation of high-

FR
FV

Phase detector

error correction signal

WINDOWN

DB

(High impedance) (High impedance)

speed locking. After the boost-up signal is output and
the PLL phase error comes within tolerance, the
boost-up circuit stops and operation continues when
the 3 supplies (V

DD1

, V

) are applied and OPR

DD2

goes HIGH once only. After the boost-up circuit
stops, new data is written and the boost-up signal is
not output even if the VCO is not in lock.

: 32fFIN

()

∗∗ ∗∗

(HIGH level output)

∗

NIPPON PRECISION CIRCUITS—7

SM5165AV

Operating principles

When the PLL is operating with a phase error within
fixed tolerance, an internal WINDOWN signal is
generated. This signal is in sync with the N counter
output signal (FV) and is 62 cycles of the FIN input
period in length centered about the falling edge of
FV.

If the phase detector error correction signal occurs
before the WINDOWN LOW-level pulse, the HIGH­level output from DB continues. However, if the
error correction signal occurs wholly within the
WINDOWN LOW-level pulsewidth, DB goes high
impedance and the boost-up circuit operation stops.

The above description applies when the error correc­tion signal is revising up. When the error correction
signal is revising down, DB goes LOW.

Standby Mode

The SM5165AV enters standby mode when OPR
goes LOW. In this mode, the following pin states and
functions occur.

Function State

Outputs DO and
DB

Phase detector Reset
Input FIN Feedback resistor is cutoff (internal HIGH level)
Input XIN Feedback resistor is cutoff (internal HIGH level)
N counter Reset
R counter Reset
Latch data Stored

Note that even in standby mode, some current flows
into VDD1 (FIN and XIN prescaler current). It is
recommended that VDD1 be grounded in standby
mode to reduce current consumption if necessary.

Note also that the above pin states and functions are
only valid if V
normal operating conditions. If V

Floating (high impedance)

and V

DD2

DD3

are maintained within

and/or V

DD2

DD3

are not within normal operating conditions, the latch data is not retained.

Phase Comparator Timing Diagram

FR

FV

DO

LD

FV and FR are the internal comparator frequency divider output signal and reference frequency divider output signal, respectively.

Passive Low-pass Filter

R1

DO

R2
C

VCO

NIPPON PRECISION CIRCUITS—8

SM5165AV

Input/Output Equivalent Circuits

XIN, XOUT DO (for passive filter)

Lagging Phase

XOUT

From

Internal

Circuit

XIN

Circuit

Internal

Circuit

Intenal

From

VDD1

VDD1

To
Internal
Counter

DB

VDD1

Transistor
Resistor

Correction Signal

Leading Phase

Correction Signal

From

Internal

Circui

From

Internal

Circui

VDD2

V

DD2

DO

DB

RO FIN

VDD2

From

Internal

Circuit

RO (FV, FR)

(for TEST mode)

OPR, CLK, DATA, LE TEST

VDD2

OPR
CLK

DATA

To
Intenal
Circuit

LE

From

Internal

Circuit

FIN1

TEST

Transistor Resistor

VDD1

VDD1

VDD1

To
Internal
Counter

Diffused Resistor

VDD1

To
Intenal
Circuit

NIPPON PRECISION CIRCUITS—9

SM5165AV

NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warr anty that such applications will be suitab le for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.

NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome

Koto-ku, Tokyo 135-8430, Japan

NIPPON PRECISION CIRCUITS INC.

Telephone: [phone]
Facsimile: 03-3642-6698

NC9609BE 1997.08

NIPPON PRECISION CIRCUITS—10