Page 1
SL74LV374
System Logic
OCTAL D-TIME FLIP-FLOP; POSITIVE EDGETRIGGER (3-StatE)
SL74LV374 are compatible by pinning with SL74HC374 and
SL74HCT374 series. Input voltage levels are compatible with
standard CMOS levels.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS.
• Supply voltage range from 2.0 to 3.2 V
• LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Output current 8 mÀ
• Latch current value not less than 150 mÀ at Ò = 125 °Ñ
• ESD acceptable values: not less than 2000 V as per HBM,
and not less than 200 V as per MM
BLOCK DIAGRAM
ORDERING INFORMATION
SL74LV374N Plastic DIP
SL74LV374D SOIC
TA = -40° to 125° C
for all packages
OE
CP
03
D
0
04
D
1
07
D
2
08
D
3
13
D
4
D
5
17
D
6
D
7
11
01
02
05
06
09
12
1514
16
1918
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
PIN ASSIGNMENT
OE
01
Q
02
0
D
03
0
D
04
1
Q
05
GND
1
Q
06
2
D
07
2
D
08
3
Q
09
3
10
374
20
V
CC
Q
19
7
D
18
7
17
D
6
Q
16
6
Q
15
5
14
D
5
D
13
4
Q
12
4
11
CP
Pin 20=VCC
Pin 10 = GND
OE CP Dn Qn
L
L
L L, H, X no change
H X X Z
FUNCTION TABLE
Inputs Output
H H
L L
SLS
Semiconductor
Page 2
SL74LV374
System Logic
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Rating Unit
VCC Supply voltage -0.5 to +5.0 V
IIK *1 Input diode current ±20 mÀ
IOK *2 Output diode current ±50 mÀ
IO *3 Output source or sink current ±35 mÀ
ICC Bus driver outputs ±70 mÀ
I
Ground current ±70 mÀ
GND
PD Power dissipation per package,
Plastic DIP *4
SOIC *4
Tstg Storage temperature range -65 to +150 °C
*
In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the absolute
maximum ratings functioning is guaranteed at the recommended operating conditions.
*1 Provide VI < -0.5 V or VI > VCC + 0.5 V.
*2 Provide VO < -0.5 V or VO > VCC + 0.5 V.
*3 Provide -0.5 V < VO < VCC + 0.5 V.
*4 When operating in the temperature range of 70°C to 125°C power dissipation value decreases
- for Plastic DIP by 12 mW/°C
- for SOIC by 8 mW/°C
750
500
mW
RECOMMENDED OPERATING MODES
Symbol Parameter Min Max Unit
VCC Supply voltage 1.2 3.6 V
VIN Input voltage 0 VCC V
V
Output voltage 0 VCC V
OUT
TA Operating ambient temperature range.
For all types packages
tLH, tHL Input rise and fall times VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
V
=3.6 V
CC
-40 125 °C
0 1000
700
500
400
ns
SLS
Semiconductor
Page 3
System Logic
DC CHARACTERISTICS
Test VCC, Limits
SL74LV374
Symbol Parameter coditions V 25°C -40°C to
85°C
min max min max min max
VIH HIGH level input
voltage
VIL LOW level input
voltage
VOH HIGH level
output voltage
VI = VIH or VIL
VOL LOW level
output voltage
VI = VIH or VIL
VO = VCC-0.1 V 1.2
2.0
3.0
3.6
VO =0.1 V 1.2
2.0
3.0
3.6
VI = VIH or VIL
IO = -50 µÀ
IO = -8 mÀ
VI = VIH or VIL
IO = 50 µÀ
IO = 8 mÀ
1.2
2.0
3.0
3.6
3.0 2.48 - 2.34 - 2.20 - V
1.2
2.0
3.0
3.6
3.0 - 0.33 - 0.4 - 0.5 V
0.9
1.4
2.1
2.5
-
-
-
-
1.1
1.92
2.92
3.52
-
-
-
-
-
-
-
-
0.3
0.6
0.9
1.1
-
-
-
-
0.09
0.09
0.09
0.09
0.9
1.4
2.1
2.5
-
-
-
-
1.0
1.9
2.9
3.5
-
-
-
-
0.3
0.6
0.9
1.1
0.1
0.1
0.1
0.1
125°C Unit
-
0.9
-
1.4
-
2.1
-
2.5
-
-
-
-
-
1.0
-
1.9
-
2.9
-
3.5
-
-
-
-
0.3
0.6
0.9
1.1
0.1
0.1
0.1
0.1
-
-
-
-
-
-
-
-
V
V
V
V
II Input leakage
current
IOZ Output OFF-
state current
ICC Suply current VI =VCC or 0 V
VI = VCC èëè
0 V
3-state outputs
VI = V
VO =VCC or 0 V
IO = 0 µÀ
IL
or V
3.6 - ±0.1 - ±1.0 - ±1.0 µÀ
3.6 - ±0.5 - ±5 - ±10 µÀ
IH
3.6 - 8.0 - 80 - 160 µÀ
SLS
Semiconductor
Page 4
SL74LV374
System Logic
AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)
Test VCC, Limits
Symbol Parameter conditions V 25°C -40°C to
min max min max min max
t
PHL, tPLH
from CP to Qn
t
PHZ tPLZ
from OE to Qn
t
PZH tPZL
from OE to Qn
t
THL, tTLH
tW Clock pulse
tSU Set-up time Dn
Propagation
delay
Propagation
delay
Propagation
delay
HIGH-to-LOW
and LOW -toHIGH transition
time
width HIGH or
LOW
to CP
Figure 1 1.2
2.0
3.0
Figure 3 1.2
2.0
3.0
Figure 3 1.2
2.0
3.0
Figure 1 1.2
2.0
3.0
Figure 1 1.2
2.0
3.0
Figure 2 1.2
2.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
250
18
11
45
13
8
180
45
27
160
38
25
160
38
23
75
16
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
350
23
14
50
17
10
85°C
230
200
200
100
56
34
57
36
48
29
20
13
-
-
-
-
-
-
125°C Unit
-
270
-
68
-
41
-
240
-
68
-
43
-
240
-
58
-
35
-
120
-
24
-
15
540
28
17
100
20
12
-
-
-
-
-
-
ns
tH Hold time Dn to
CP
fc CP naximum
pulse frequency
CI Input
capacitance
CPD Power
dissipation
capacitance (per
flip-flop)
Figure 2 1.2
Figure 1 2.0
3.0 - 7 - - - - pF
VI = 0 V or VCC 3.0 - 34 - - - -
25
2.0
3.0
3.0 - -
5
5
-
25
-
-
27
46 - -
5
5
-
25
-
-
22
37 - -
5
5
-
-
-
18
31
MHz
SLS
Semiconductor
Page 5
SL74LV374
System Logic
t
LH
0.9
V
CC
CP
Qn
0.1
V1 = 0.5V
CC
V
1
t
PLH
0.1
V
1
t
W
1/fc
0.9
V
1
t
TLH
Figure 1- Time diagram
V
1
t
0.9
PHL
t
THL
GND
V
1
0 B
0.1
V
V
CC
Dn
CP
V
1
t
SU
V1 = 0.5V
V
1
t
H
V
1
CC
Figure 2 - Time diagram
V
1
V
1
GND
t
SU
t
H
V
CC
V
1
GND
SLS
Semiconductor
Page 6
SL74LV374
System Logic
OE
Qn
Qn
0.1
t
LH
0.9
V
1
t
PZH
V
1
V
1
t
PZL
t
HL
V
CC
0.9
V
1
0.1
GND
V
OH
0.9
t
PHZ
V
0 B
V
t
PLZ
CC
0.1
V
OL
V1 = 0.5V
CC
Figure 3 - Time diagram
SLS
Semiconductor
Page 7
System Logic
Drawing of the chip
SL74LV374
1.66 mm
18
19
17
16
1415
13
12
20
11
74LV373/374
1.68 mm
1
2
3
On-chip marking
4
5
6 7 8
10
9
Pads allocation Table
coordinates (counted from lower left corner), mm Pad
number
01 0.142 0.628 0.108 x 0.108
02 0.142 0.377 0.108 x 0.108
03 0.142 0.125 0.108 x 0.108
04 0.498 0.125 0.108 x 0.108
05 0.693 0.125 0.108 x 0.108
06 0.871 0.125 0.108 x 0.108
07 1.095 0.125 0.108 x 0.108
08 1.423 0.130 0.108 x 0.108
09 1.423 0.329 0.108 x 0.108
10 1.423 0.587 0.108 x 0.108
11 1.423 0.949 0.108 x 0.108
12 1.423 1.198 0.108 x 0.108
13 1.423 1.447 0.108 x 0.108
14 1.085 1.447 0.108 x 0.108
15 0.868 1.447 0.108 x 0.108
16 0.696 1.447 0.108 x 0.108
17 0.461 1.447 0.108 x 0.108
18 0.142 1.447 0.108 x 0.108
19 0.142 1.245 0.108 x 0.108
20 0.142 0.997 0.108 x 0.108
X Y
Pad size, mm
SLS
Semiconductor
Page 8
SL74LV374
System Logic
SLS
Semiconductor
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