Datasheet SL74LV32, SL74LV32D, SL74LV32N Datasheet (SLS)

TECHNICAL DATA

Semiconductor

Quad 2-Input OR Gate

The SL74LV32 is low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT32A.

The SL74LV32 provides the 2-input AND function.

• Optimized for Low Voltage applications: 1.2 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Low Input Current

SL74LV32

ORDERING INFORMATION

SL74LV32N Plastic SL74LV32D SOIC IZ74LV32 Chip

TA = -40° ÷ 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

A1

B1

Y1

A2

B2

Y2

A3 B3

A4

B4

PIN 14 =VCC

PIN 7 = GND

Y3

Y4

FUNCTION TABLE

Input Output

A B Y = A*B

L L L

L H H H L H H H H

H - high level L - low level

SLS

System Logic

1

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC supply voltage (Referenced to GND) -0.5 ÷ +5.0 V

IIK *1 DC input diode current ±20 mA

IOK *2 DC output diode current ±50 mA

SL74LV32

IO *3 DC output source or sink current

±25 mA

-bus driver outputs

ICC DC VCC current for types with

±50 mA

- bus driver outputs

I

DC GND current for types with

GND

±50 mA

- bus driver outputs

PD Power dissipation per package, plastic DIP+

SOIC package+

750 500

Tstg Storage temperature -65 ÷ +150 °C

TL Lead temperature, 1.5 mm from Case for 10 se conds

260 °C

(Plastic DIP ), 0.3 mm (SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SOIC Package: : - 8 mW/°C from 70° to 125°C

*1: VI < -0.5V or V

> VCC+0.5V

I

*2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V

RECOMMENDED OPERATING CONDITIONS

mW

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 1.2 3.6 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -40 +125 °C

tr, tf Input Rise and Fall Time VCC =1.2 V

VCC =2.0 V V

=3.0 V

CC

V

=3.6 V

CC

0 0 0 0

1000

700 500 400

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V V

)≤VCC.

OUT

should be constrained to the range GND≤(VIN or

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

SLS

System Logic

2

Semiconductor

put

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

SL74LV32

Symbol Parameter Test Conditions

VIH High-Level Input

Voltage

VIL Low -Level Input

Voltage

1.2

VI = VIL or VIH IO = -50 µÀ

VI = VIL or VIH IO = -6.0 mÀ

VI = VIL or VIH IO = 50 µÀ

VCC,

V

min max min max min max

2.0

3.0

3.6

2.0

3.0

3.6

1.2

2.0

3.0

3.6

3.0 2.48 - 2.34 - 2.20 - V

1.2

2.0

3.0

3.6

25°C -40°C ÷ 85°C -40°C ÷

0.9

1.4

2.1

2.5

-

1.1

1.92

2.92

3.52

-

Guaranteed Limit

-

0.9

-

1.4

-

2.1

-

2.5

0.3

0.6

0.9

1.1

0.09

-

1.0

-

1.9

-

2.9

-

3.5

-

0.3

0.6

0.9

1.1

-

0.1

125°C

0.9

1.4

2.1

2.5

-

1.0

1.9

2.9

3.5

-

0.3

0.6

0.9

1.1

-

0.1

Unit

V

V VOH High-Level Out

V VOL Low-Level Output

IIL Low-Level Input

Leakage Current

IIÍ High-Level Input

Leakage Current

IÑÑ Quiescent Supply

Current (per Package)

VI = VIL or VIH IO = 6.0 mÀ

VI = 0 V 3.6 - -0.1 - -1.0 - -1.0

VI = VCC 3.6 - 0.1 - 1.0 - 1.0

VI = 0 Â or V IO = 0 µÀ

CC

3.0 - 0.33 - 0.4 - 0.5 V

3.6 - 2.0 - 20 - 40

µA

SLS

System Logic

3

SL74LV32

Semiconductor

AC ELECTRICAL CHARACTERISTICS (C

Symbol Parameter

VCC

V

=50 pF , tLH = tHL = 6.0 ns, V

L

= 0V, VIH=VCC, RL=1k)

IL

Guaranteed Limit

25°C -40°C ÷ 85°C -40°C ÷ 125°C

min max min max min max

t

(t

t

THL,

PHL,

) Output Transition

TLH

Time, Any Output (Figure 1)

(t

Propagation Delay,

PLH)

Input A to Output Y (Figure 1)

1.2

2.0 *

1.2

2.0 *

-

60 16 10

125

20 12

-

75 20 13

360

25 15

-

CI Input Capacitance 3.0 - 7.0 - - - - pF

CPD Power Dissipation Capacitance (Per Gate)

ÒÀ=25°Ñ, VI=0V÷VCC

44

90 24 15

360

30 18

Unit

ns

pF

* - VCC= (3.3±0.3) V P

= CPDV

D

(CLV

2

fI+ (CLV

CC

2

fo) – sum of the outputs

CC

PULSE

GENERATOR

t

L H

Input À, B

0.1 0.1

Output Y

V = 0.5 V

1 CC

2

fo), fI-input frequency, fo- output frequency (MHz)

CC

0.9

V

1

t

P LH

V

1

0.1

t

T LH

t

HL

0.9 V

1

t

P H L

0.9

Figure 1. Switching Waveforms

V

C C

V

I

DEVICE

UNDER

TEST

R

T

V

O

C

L

V

C C

GND

V

OH

V

1

0.1

T

T HL

V

OL

Termination resistance RT -

R

should be equal to Z

L

generators

OUT

pulse

SLS

System Logic

4

SL74LV32

Semiconductor

Figure 2. Test Circuit

SLS

System Logic

5

Semiconductor

CHIP PAD DIAGRAM SL74LV32

SL74LV32

101112

13

09

08

14

±

07

1.20 0.03

01 02

03

1.23 0.03

Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm

PAD LOCATION

Pad No Symbol X Y

04 05

±

06

Chip marking

25LV32

(x=1.009; y=0.727

)

01 A1 0.111 0.287 02 B1 0.111 0.119 03 Y1 0.504 0.111 04 A2 0.672 0.111 05 B2 1.009 0.111 06 Y2 1.009 0.277 07 GND 1.009 0.447 08 Y3 1.009 0.806 09 A3 1.009 0.974 10 B3 0.672 0.974 11 Y4 0.504 0.974 12 A4 0.336 0.974 13 B4 0.111 0.772 14 Vcc 0.111 0.618

SLS

System Logic

6