Datasheet SL74LV14, SL74LV14D, SL74LV14N Datasheet (SLS)

TECHNICAL DATA

Semiconductor

SL74LV14

Hex Schmitt-Trigger Inverter

The 74LV14 is a low -voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT14.

The 74LV14 provides six inverting buffers with Schmitt-trigger action.

• Wide Operating Voltage: 1.0 to 5.5 V

• Optimized for Low Voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V

• Low input current

LOGIC DIAGRAM

ORDERING INFORMATION

SL74LV14N Plastic SL74LV14D SOIC SL74LV14 Chip

TA = -40° ÷ 125° C for all packages

PIN ASSIGNMENT

FUNCTION TABLE

Input Output

A

L H

H L

PIN 14 =VCC PIN 7 = GND

Y= A

SLS

System Logic

1

SL74LV14

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC supply voltage (Referenced to GND) -0.5 ~ +7.0 V

IIK*1 DC input diode current ±20 mA

IOK*2 DC output diode current ±50 mA

Io*3 DC output source or sink current

±25 mA

-bus driver outputs

I

DC GND current for types with

GND

±50 mA

- bus driver outputs

ICC DC VCC current for types with

±50 mA

- bus driver outputs

PD Power dissipation per paskade, plastic DIP+

SOIC package+

750 500

Tstg Storage temperature -65 ~ +150 °C

TL Lead temperature, 1.5 mm from Case for 10 seconds

260 °C

(Plastic DIP ), 0.3 mm (SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SOIC Package: : - 8 mW/°C from 70° to 125°C

*1: VI < -0.5V or V

> VCC+0.5V

I

*2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V

RECOMMENDED OPERATING CONDITIONS

mW

Symbol Parameter Min Max Unit

VCC DC Supply Vol tage (Referenced to GND) 1.0 5.5 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -40 +125 °C

tr, tf Input Rise and Fall Time 1.0 V ≤VCC <2.0 V

2.0 V ≤VCC <2.7 V

2.7 V ≤VCC <3.6 V

3.6 V ≤VCC ≤5.5 V

0 0 0 0

500 200 100

50

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

System Logic

SLS

2

Semiconductor

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

SL74LV14

Symbol Parameter

VIT+ Positive-Going

Input Threshold Voltage

VIT- Negative-Going

Input Threshold Voltage

VH Hysteresis

Voltage

VOH High-Level

Output Voltage

Test

Conditions

VCC

V

VO ≥ VOH 1.2

2.0

2.7

3.0

3.6

4.5

5.5

VO ≤ VOL 1.2

2.0

2.7

3.0

3.6

4.5

5.5

VO ≥ V

OH

VO ≤ VOL

1.2

2.0

2.7

3.0

3.6

4.5

5.5

VI = V V

IO = -100 µA

–or

IH

IL

1.2

2.0

2.7

3.0

3.6

4.5

5.5

Guaranteed Limit

25°C -40°C ÷ 85°C -40°C ÷ 125°C

min max min max min max

0.45

0.85

1.05

1.25

1.55

1.75

2.15

0.2

0.35

0.45

0.65

0.85

0.95

1.15

0.2

0.25

0.35

0.45

0.65

1.05

1.85

2.55

2.85

3.45

4.35

5.35

0.95

1.35

1.95

2.15

2.35

3.10

3.80

0.65

0.85

1.35

1.45

1.75

1.95

1.15

0.65

0.75

1.05

1.15

1.35

1.45

-

0.4

0.8

1.0

1.2

1.5

1.7

2.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

1.0

1.8

2.5

2.8

3.4

4.3

5.3

1.0

1.4

2.0

2.2

2.4

3.15

3.85

0.7

0.9

1.4

1.5

1.8

2.0

2.26

0.7

0.9

1.4

1.5

1.8

2.0

2.6

-

0.4

0.8

1.0

1.2

1.5

1.7

2.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

1.0

1.8

2.5

2.8

3.4

4.3

5.3

1.0

1.4

2.0

2.2

2.4

3.15

3.85

0.7

0.9

1.4

1.5

1.8

2.0

2.26

0.7

0.9

1.4

1.5

1.8

2.0

2.6

-

Unit

V

VOL Low-Level

SLS

Output Voltage

System Logic

VI = V V

–or

IH

IL

IO = -6.0 mA

VI = V V

–or

IH

IL

IO = -12.0 mA

VI = V V

–or

IH

IL

IO = 100 µA

3.0 2.48 - 2.40 - 2.20 - VOH High-Level

4.5 3.70 - 3.60 - 3.50 -

1.2

2.0

2.7

3.0

3.6

4.5

5.5

-

0.15

-

0.15

-

0.15

-

0.15

-

0.15

-

0.15

-

0.15

-

0.2

-

0.2

V

3

Semiconductor

DC ELECTRICAL CHARACTERISTICS (continuation)

SL74LV14

Symbol Parameter

Output Voltage

IIL Low-Level Input

Leakage Current

IIH High-Level

Input Leakage Current

ICC Quiescent

Supply Current (per Package)

I

Additional

CC1

Quiescent Supply Current on input

Test

Conditions

VCC

V

25°C -40°C ÷ 85°C -40°C ÷ 125°C

Guaranteed Limit

Unit

min max min max min max

VI = V

IH

–or

3.0 - 0.33 - 0.40 - 0.50 VOL Low-Level

IO = 6.0 mA VI = V

V

–or

IH

IL

4.5 - 0.40 - 0.55 - 0.65

IO = 12.0 mA

VI=0 V 5.5 - -0.1 - -1.0 - -1.0

µA

VI= VÑÑ 5.5 - 0.1 - 1.0 - 1.0

VI=0 Â or V

ÑÑ

5.5 - 4.0 - 20 - 40

µA

IO = 0 µA VI = V

0.6V

-

ÑÑ

2.7

- 0.2 - 0.5 - 0.85 mA

3.6

IO = 0 µA

V

.

SLS

System Logic

4

SL74LV14

Semiconductor

AC ELECTRICAL CHARACTERISTICS (C

Symbol Parameter

t

, t

PLH

Propagation

PHL

Delay, Input A to Output Y (Figure 1 )

CI Input

Capacitance

CPD VI=0 V or

Input À

Test

Conditions

VI=0 V or V

1

tLH = tHL =2.5 ns ÑL = 50 pF RL = 1 kÙ

5.5

VÑÑ

t

HL

0.1

VCC

V

1.2

2.0

2.7

3.0

4.5

5.5

0.9

V

X

t

P HL

=50 pF, tLH =tHL = 2.5 ns, RL=1 kÙ)

L

Guaranteed Limit

25°C -40°C ÷ 85°C -40°C ÷ 125°C

min max min max min max

-

150

-

28 22 17 14

-

170

-

37 28 22 18

-

- 7.0 - 7.0 - 7.0

- 30 - 30 - 30

t

LH

V

0.9 V

X

0.1

t

PL H

1

GND

200

48 35 28 23

Unit

ns

pF

GENERATOR

Output Y

PULSE

V

OH

V

Y

VX=0.5 V

CC

V

Y

V

O L

Figure 1. Switching Waveforms

V

C C

V

I

DEVICE

UNDER

R

TEST

T

V

O

C

L

Termination resistance RT – should be equal to Z generators

R

L

of pulse

OUT

Figure 2. Test Circuit

SLS

System Logic

5

Semiconductor

1.42 0.03

±

1.33 0.03

±

CHIP PAD DIAGRAM SL74LV14

SL74LV14

13

14

12

1011

09

08

07

01

02

03

Chip marking

IN74LV14

(x=0.130; y=0.130

Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 ± 0,02 mm

04 05 06

)

PAD LOCATION

Pad No Symbol X Y

01 A1 0.130 0.463 02 Y1 0.130 0.230 03 A2 0.381 0.126 04 Y2 0.616 0.126 05 A3 0.881 0.126 06 Y3 1.116 0.126 07 GND 1.115 0.631 08 Y4 1.115 0.846 09 A4 1.115 1.181 10 Y5 0.804 1.194 11 A5 0.569 1.194 12 Y6 0.378 1.194 13 A6 0.143 1.194 14 VCC 0.130 0.813

SLS

System Logic

6