Page 1
Semiconductor
3-TO-8 DECODER/DEMULTIPLEXER
By pinning SL74LV138 are compatible with SL74HC138 and
SL74HCT138 series. Input voltage levels are compatible with
standard CMOS ones.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Supply vo ltage range is from 1.2 to 5.5 V
• Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Output current 6 mÀ
• Latch current is not less than 150 mÀ at Ò = 125 °Ñ
• ESD acceptable values: than 2000 V as per HBM, and not less
than 200 V as per MM
BLOCK DIAGRAM
Y0
ORDERING INFORMATION
SL74LV138N Plastic DIP
SL74LV138D SOIC
TA = -40° to 125° C
for all packages
SL74LV138
A0
A1
A2
CS3
CS2
CS1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CS2
X X H X X X H H H H H H H H
X H X X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L
INPUTS OUTPUTS
A2 A1 A0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
FUNCTION TABLE
PIN ASSIGNMENT
A0
A1
A2
CS2
Cs3
CS1
Y7
1
2
3
4
5
6
7
8GND
16
15
14
13
12
11
10
9
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
CC
SLS
System Logic
Page 2
SL74LV138
Semiconductor
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Rating Unit Conditions
Vcc Supply voltage -0.5 to +7.0 V
Iik Input diode current ±20 mA VI<-0.5 V orVI>Vcc>+0.5 V
Iok Output diode current ±50 mA V0<-0.5 V or VI>Vcc>+0.5 V
Io Output current standard output ±25 mÀ -0.5 V<Vo<Vcc+0.5 V
Icc DC Vcc, standard output ±50 mÀ
I
GND current ±50 mÀ
GND
Tstg Starage temperature range -65 to +150
PD Power dissipation per package:
DIP
SO
Notes:
Power dissipation value decreases for:
DIP - 12 mW°C in the range from 70 to 125°Ñ
SO - 8 mW°C in the range from 70 to 125°Ñ
750
500
î
Ñ
mW
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit Conditions
Vcc Supply voltage 1.2 5.5 V
VI Input voltage 0 Vcc V
Vî Output voltage 0 Vcc V
T Ambient temperature range -40 +125
tr,tf Input rise and fall times 500
200
100
50
o
C
ns/V Vcc= 1.0 ÷ 2.0 V
Vcc= 2.0 ÷ 2.7 V
Vcc= 2.7 ÷ 3.6 V
Vcc= 3.6 ÷ 5.5 V
SLS
System Logic
Page 3
SL74LV138
Semiconductor
DC CHARACTERISTICS
Sym Conditions Limits
bol Parameter Vcñ VI -40 to +25°C +85 îÑ +125 îÑ Unit
(V) Min Max Min Max Min Max
VIH HIGH level
input voltage
VIL LOW level
output
voltage
VOH HIGH level
output
voltage
VOH HIGH level
output
voltage;
standard
outputs
VOL LOW level
output
voltage
1.2
2.0
2.7 to 3.6
4.5 to 5.5
1.2
2.0
2.7 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.6
5.5
3.0
4.5
1.2
2.0
2.7
3.6
5.5
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
V
IO =-100 µÀ 1.05
IH
or
VIL
V
IO =-6 mA
IH
or
IO =-12 mA
VIL
V
IO =100µÀ -
IH
or
VIL
1.85
2.55
3.45
5.35
2.48
3.70
-
-
-
-
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
1.0
1.8
2.5
3.4
5.3
2.40
3.60
-
-
-
-
-
-
-
-
-
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.9
1.4
2.0
0.7 Vcc
-
-
-
-
1.0
1.8
2.5
3.4
5.3
2.20
3.50
-
-
-
-
-
-
-
-
--
0.3
0.6
0.8
0.3 Vcc
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
V
V
V
V
V
VOL LOW level
output
voltage;
standard
outputs
II Input leakage
current
Icc Supply
current
Icc Additional
supply
current per
input
3.0
4.5
5.5 Vññ
5.5 Vññ
2.7 äî 3.6 VI = Vcc-0.6V - 0.2 0.5 - 0.85 mA
V
IO =6 mA
IH
or
IO =12 mA
VIL
- ±1.0 ±1.0 - ±1.0 µÀ
or
GND
Io = 0 8.0 80 160 µÀ
or
GND
-
0.33
-
0.40
-
0.40
-
0.55
-
0.50
-
0.65
V
System Logic
SLS
Page 4
SL74LV138
Semiconductor
AC CHARACTERISICS (C
=50 pF, RL=1 KΩ, tLH = tHL = 2.5 ns
L
Sym Conditions Limits
t
from An to
t
from CS to
bol Parameter Vcc -40 to +25°C
Min Max Min Max Min Max
, t
PHL
Yn
, t
PHL
Yn
CI Input
PLH
PLH
Propagation
delay
Propagation
delay
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
VI = Vcc or
GND
-
150
-
33
-
23
-
19
-
14
-
170
-
35
-
26
-
21
-
17
5.0 Ò=+25 îÑ 7.0 - ns
+85°C +125°C Unit
-
150
-
36
-
26
-
21
-
16
-
170
-
39
-
29
-
23
-
19
capacitance
CPD Power
dissipation
capacitance
Ò=+25 îÑ
VI = Vcc or
GND
134 - ns
per package
-
150
-
44
-
33
-
26
-
20
-
170
-
49
-
36
-
29
-
24
ns
ns
SLS
System Logic
Page 5
Semiconductor
Drawing of the chip
1.4 mm
1.33 mm
SL74LV138
15
16
1
14
74LV138
1213
On-chip marking
1011
9
8
7
2
3
4 5
6
Pads allocation Table
coordinates (counted from lower left corner), mm Pad
number
01 0.1415 0.6270 0.100 x 0.100
02 0.1415 0.3880 0.100 x 0.100
03 1.1375 0.1515 0.100 x 0.100
04 0.4535 0.1190 0.100 x 0.100
05 0.6245 0.1190 0.100 x 0.100
06 0.7800 0.1190 0.100 x 0.100
07 0.9520 0.1180 0.100 x 0.100
08 1.2685 0.1185 0.100 x 0.100
09 1.2480 0.2960 0.100 x 0.100
10 1.2650 0.5160 0.100 x 0.100
11 1.2650 0.8430 0.100 x 0.100
12 1.2425 1.0820 0.100 x 0.100
13 1.2465 1.3165 0.100 x 0.100
14 0.9520 1.3120 0.100 x 0.100
15 0.7800 1.3110 0.100 x 0.100
16 0.6245 1.3110 0.100 x 0.100
X Y
Pad size, mm
System Logic
SLS
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