Page 1
Semiconductor
Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The SL74HCT374 is identical in pinout to the LS/ALS374.
The SL74HCT374 may be used as a level converter for interfacing
TTL or NMOS outputs to High-Speed CMOS inputs.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of the Clock. The Output Enable input does not affect
the states of the flip-flops, but when Output Enable is high, the
outputs are forced to the high-impedance state; thus, data may be
stored even when the outputs are not enabled.
• TTL/NMOS-Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT374N Plastic
SL74HCT374D SOIC
TA = -55° to 125° C for all packages
SL74HCT374
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
Output
Enable
L H H
Clock D Q
SLS
L L L
L L,H, X no
change
H X X Z
X = don’t care
Z = high impedance
System Logic
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SL74HCT374
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
SL74HCT374
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VIN=VIH or V
VOL Maximum Low -Level
Output Voltage
VIN= VIL or VIH
IIN Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
IL
I
≤ 6.0 mA
OUT
VIN= VIL or VIH
I
≤ 20 µA
OUT
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
I
≤ 6.0 mA
OUT
4.5 0.26 0.33 0.4
VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
Leakage Current
IOZ Maximum Three State
Leakage Current
ICC Maximum Quiescent
Supply Current
Output in High-Impedance
State
VIN =VIH or V
V
OUT=VCC
IL
or GND
VIN=VCC or GND
I
=0µA
OUT
5.5 ±0.5 ±5.0 ±10 µA
5.5 4.0 40 160 µA
(per Package)
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
Unit
V
V
V
V
∆ICC Additional Quiescent
Supply Current
I
System Logic
SLS
VIN=2.4 V, Any One Input
VIN=VCC or GND,
≥-55°C 25°C to
125°C
Other Inputs
=0µA 5.5 2.9 2.4
OUT
mA
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SL74HCT374
Semiconductor
AC ELECTRICAL CHARACTERISTICS(V
=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
CC
Guaranteed Limit
Symbol Parameter 25 °C to
≤85°C ≤125°C Unit
-55°C
f
Maximum Clock Frequency (50% Duty Cycle)
max
30 24 20 MHz
(Figures 1 and 4)
t
, t
PLH
Maximum Propagation Delay, Clock to Q (Figures
PHL
31 39 47 ns
1 and 4)
t
, t
PLZ
Maximum Propagation Delay, Output Enable to Q
PHZ
30 38 45 ns
(Figures 2 and 5)
t
, t
PZH
Maximum Propagation Delay, Output Enable to Q
PZL
30 38 45 ns
(Figures 2 and 5)
t
, t
TLH
Maximum Output Transition Ti me, Any Output
THL
12 15 18 ns
(Figures 1 and 4)
CIN Maximum Input Capacitance 10 10 10 pF
C
Maximum Three-State Output Capacitance
OUT
15 15 15 pF
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Flip-Flop) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
TIMING REQUIREMENTS (V
2
f+ICCVCC
CC
=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
CC
65 pF
Guaranteed Limit
Symbol Parameter 25 °C to
≤85°C ≤125°C Unit
-55°C
tSU Minimum Setup Time, Data to
12 15 18 ns
Clock (Figure 3)
th Minimum Hold Time, Clock to
5.0 5.0 5.0 ns
Data (Figure 3)
tw Minimum Pulse Width, Clock
12 15 18 ns
(Figure 1)
t
Maximum Input Rise and Fall
r, tf
500 500 500 ns
Times (Figure 1)
SLS
System Logic
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SL74HCT374
Semiconductor
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
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