Page 1
Semiconductor
Quad 3-State Noninverting Buffers
SL74HCT125
High-Performance Silicon-Gate CMOS
The SL74HCT125 is identical in pinout to the LS/ALS125. The
SL74HCT125 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The SL74HCT125 noninverting buffers are designed to be used with
3-state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are activelow.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HCT125N Plastic
SL74HCT125D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
SLS
System Logic
PIN 14 =V
PIN 7 = GND
CC
FUNCTION TABLE
Inputs Output
A OE Y
H L H
L L L
X H Z
X = don’t care
Z = high impedance
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SL74HCT125
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which dam age to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. Fo r proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
SL74HCT125
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VIN=VIH
VOL Maximum Low -Level
Output Voltage
VIN=VIL
IIN Maximum Input
V
= VCC-0.1 V
OUT
I
≤ 20 µA
OUT
V
=0.1 V
OUT
I
≤ 20 µA
OUT
VIN=VIH
I
≤ 20 µA
OUT
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
I
≤ 6.0 mA
OUT
VIN=VIL
I
≤ 20 µA
OUT
4.5 3.98 3.84 3.7
4.5
5.5
0.1
0.1
I
≤ 6.0 mA
OUT
4.5 0.26 0.33 0.4
VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
Leakage Current
IOZ Maximum Three-State
Leakage Current
Output in High-Impedance
State
5.5 ±0.5 ±5.0 ±10 µA
VIN=VIL or VIH
VIN=VCC or GND
≤85
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
≤125
°C
2.0
2.0
0.8
0.8
4.4
5.4
0.1
0.1
Unit
V
V
V
V
ICC Maximum Quiescent
Supply Current
(per Package)
∆ICC Additional Quiescent
Supply Current
I
System Logic
SLS
VIN=VCC or GND
I
=0µA
OUT
VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other
5.5 4.0 40 160 µA
≥-55°C 25°C to
125°C
Inputs
=0µA 5.5 2.9 2.4
OUT
mA
Page 4
SL74HCT125
Semiconductor
AC ELECTRICAL CHARACTERISTICS(V
=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
CC
Guaranteed Limit
Symbol Parameter 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
PLH
Maximum Propagation Delay, Input A to
PHL
18 23 27 ns
Output Y (Figures 1 and 3)
t
, t
PLZ
Maximum Propagation Delay, Output Enable toY
PHZ
24 30 36 ns
(Figures 2 and 4)
t
, t
PZL
Maximum Propagation Delay, Output Enable toY
PZH
18 23 27 ns
(Figures 2 and 4)
t
, t
TLH
Maximum Output Transition Time, Any Output
THL
12 15 18 ns
(Figures 1 and 3)
CIN Maximum Input Capacitance 10 10 10 pF
C
Maximum Three-State Output Capacitance
OUT
15 15 15 pF
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Buffer) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
2
f+ICCVCC
CC
48 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
System Logic
SLS
Page 5
SL74HCT125
Semiconductor
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
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