Datasheet SL74HC640D, SL74HC640N Datasheet (SLS)

Semiconductor

Octal 3-State Inverting Bus Transceiver

High-Performance Silicon-Gate CMOS

The SL74HC640 is identical in pinout to the LS/ALS640. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The SL74HC640 is a 3-state transceiver that is used for 2-way asynchronous communication between data buses. The device has an active-low Output Enable pin, which is used to place the I/O ports into high-impedance states. The Direction control determines whether data flows from A to B or from B to A.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC640N Plastic

SL74HC640D SOIC

TA = -55° to 125° C for all packages

SL74HC640

LOGIC DIAGRAM

PIN 20=VCC

PIN 10 = GND

PIN ASSIGNMENT

FUNCTION TABLE

Control Inputs

Output

Enable

L L Data Transmitted

Direction Operation

from Bus B to Bus A (inverted)

SLS

L H Data Transmitted

from Bus A to Bus B (inverted)

H X Buses Isolated

(High Impedance State)

X = don’t care

System Logic

SL74HC640

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Sti ll Air, Plastic DIP+

SOIC Package+

750 500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V V

=6.0 V

CC

0

1000 0 0

500 400

mW

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

System Logic

SLS

SL74HC640

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage

VIN= VIL or VIH

IIN Maximum Input

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

VIN= VIL or VIH

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.98

5.48

0.1

0.26

VIN=VCC or GND, Pin 1 or 19 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

≤85

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.84

5.34

0.1

0.33

≤125

°C

1.5

3.15

4.2

0.3

0.9

1.2

1.9

4.4

5.9

3.7

5.2

0.1

0.4

Unit

V

IOZ Maxim um Three-State

Leakage Current

ICC Maximum Quiescent

Supply Current (per Package)

System Logic

SLS

Output in High-Impedance State VIN= V V

IL

OUT=VCC

or V

IH

or GND

VIN=VCC or GND I

=0µA

OUT

6.0 ±0.5 ±5.0 ±10 µA

6.0 4.0 40 160 µA

SL74HC640

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

≤85°C ≤125°C Unit

-55°C

t

, t

t

PLH

PLZ

PZL

TLH

Maximum Propagation Delay, A to B , B to A

PHL

(Figures 1 and 3)

, t

Maximum Propagation Delay , Directi on or Output

PHZ

Enable to A or B (Figures 2 and 4)

, t

Maximum Propagation Delay , Direction or Output

PZH

Enable to A or B (Figures 2 and 4)

, t

Maximum Output Transition Time, Any Output

THL

(Figures 1 and 3)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

75 15 13

110

22 19

110

22 19

60 12 10

95 19 16

140

28 24

140

28 24

75 15 13

110

22 19

165

33 28

165

33 28

90 18 15

CIN Maximum Input Capacitance (Pin 1 or Pin 19) - 10 10 10 pF

C

Maximum Three-State I/O Capacitance

OUT

- 15 15 15 pF

(Output in High-Impedance State)

Power Dissipation Capacitance (Per Transceiver

Typical @25°C,VCC=5.0 V

Channel)

ns

CPD Used to determine the no-load dynamic power

consumption: PD=CPDV

2

f+ICCVCC

CC

40 pF

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

SLS

System Logic

SL74HC640

Semiconductor

Figure 3. Test Circuit Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

SLS

System Logic