Datasheet SL74HC595D, SL74HC595N Datasheet (SLS)

SL74HC595

Semiconductor

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

High-Performance Silicon-Gate CMOS

The SL74HC595 is identical in pinout to the LS/ALS595. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The SL74HC595 consists of an 8-bit shift register and an 8-bit Dtype latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous re set for the shift register.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC595N Plastic

SL74HC595D SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

SLS

PIN 16 =VCC

PIN 8 = GND

System Logic

SL74HC595

Semiconductor

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

V

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

OUT

IIN DC Input Current, per Pin ±20 mA

I

DC Output Current, per Pin ±35 mA

OUT

ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750 500

Tstg Storage Temperature -65 to +150 °C

TL Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, V

DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

OUT

TA Operating Temperature, All Package Types -55 +125 °C

tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V

VCC =4.5 V V

=6.0 V

CC

0 0 0

1000

500 400

mW

ns

This device contains protection circuitry to guard agai nst damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and V GND≤(VIN or V

OUT

)≤VCC.

should be constrained to the range

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

System Logic

SLS

SL74HC595

Semiconductor

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V 25 °C

to

-55°C

VIH Minimum High-Level

Input Voltage

VIL Maximum Low -Level

Input Voltage

VOH Minimum High-Level

Output Voltage, QAQH

VIN=VIH or VIL

VOL Maximum Low -Level

Output Voltage, QAQH

VIN=VIH or VIL

VOH Minimum High-Level

Output Voltage, SQH

V

=0.1 V or VCC-0.1 V

OUT

I

≤ 20 µA

OUT

V

=0.1 V or VCC-0.1 V

OUT

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

I

 ≤ 6.0 mA

OUT

I

 ≤ 7.8 mA

OUT

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.98

5.48

0.1

0.26

1.9

4.4

5.9

≤85

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.84

5.34

0.1

0.33

1.9

4.4

5.9

≤125

°C

1.5

3.15

4.2

0.5

1.35

1.8

1.9

4.4

5.9

3.7

5.2

0.1

0.4

1.9

4.4

5.9

Unit

V

VIN=VIH or VIL

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

VOL Maximum Low -Level

Output Voltage, SQH

VIN=VIH or VIL

I

 ≤ 20 µA

OUT

VIN=VIH or VIL

I

 ≤ 4.0 mA

OUT

I

 ≤ 5.2 mA

OUT

IIN Maximum Input

VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

Leakage Current

IOZ Maximum Three-State

Leakage Current, QAQH

Output in High-Impedance State VIN= VIL or VIH VIN=VCC or GND

ICC Maximum Quiescent

Supply Current

VIN=VCC or GND I

=0µA

OUT

(per Package)

System Logic

SLS

4.5

6.0

2.0

4.5

6.0

4.5

6.0

3.98

5.48

0.1

0.26

3.84

5.34

0.1

0.33

3.7

5.2

0.1

0.4

V

6.0 ±0.5 ±5.0 ±10 µA

6.0 4.0 40 160 µA

SL74HC595

Semiconductor

SLS

System Logic

SL74HC595

Semiconductor

AC ELECTRICAL CHARACTERISTICS(C

=50pF,Input tr=tf=6.0 ns)

L

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

-55°C

f

Minimum Clock Frequency (50% Duty Cycle)

max

(Figures 1and 7)

t

, t

PLH

Maximum Propagation Delay, Shift Clock to SQH

PHL

(Figures 1and 7)

t

Maximum Propagation Delay , Reset to SQH

PHL

(Figures 2 and 7)

t

, t

PLH

Maximum Propagation Delay , Latch Clock to QA-

PHL

QH (Figures 3 and 7)

t

, t

PLZ

Maximum Propagation Delay , Output Enable to

PHZ

QA-QH (Figures 4 and 8)

t

, t

PZL

Maximum Propagation Delay , Output Enable to

PZH

QA-QH (Figures 4 and 8)

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

6.0 30 35

140

28 24

145

29 25

140

28 24

150

30 26

135

27 23

≤85

°C

4.8 24 28

175

35 30

180

36 31

175

35 30

190

38 33

170

34 29

≤125

°C

4.0 20 24

210

42 36

220

44 38

210

42 36

225

45 38

205

41 35

Unit

MHz

ns

t

, t

t

TLH

Maximum Output Transition Time, QA-QH (Figures

THL

3 and 7)

, t

Maximum Output Transition Time, SQ

THL

H

(Figures 1 and 7)

2.0

4.5

6.0

2.0

4.5

6.0

60 12 10

75 15 13

95 19 16

90 18 15

110

22 19

CIN Maximum Input Capacitance - 10 10 10 pF

C

Maximum Three-State Output Capacitance

OUT

- 15 15 15 pF

(Output in High-Impedance State), QA-QH

Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V

CPD Used to determine the no-load dynamic power

consumption: PD=CPDV

2

f+ICCVCC

CC

300 pF

ns

SLS

System Logic

SL74HC595

Semiconductor

TIMING REQUIREMENTS(C

VCC Guaranteed Limit

Symbol Parameter V 25 °C to

Tsu Minimum Setup Time,Serial Data

Input A to Shift Clock (Figure 5)

Tsu Minimum Setup Time, Shift Clock to

Latch Clock (Figure 6)

th Minimum Hold Time, Shift Clock to

Serial Data Input A (Figure 5)

T

Minimum Recovery Time, Reset

rec

Inactive to Shift Clock (Figure 2)

Tw Minimum Pulse Width, Reset (Figure

2)

Tw Minimum Pulse Width, Shift Clock

(Figure 1)

=50pF,Input tr=tf=6.0 ns)

L

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

-55°C

50 10

9

75 15 13

5 5 5

50 10

9

60 12 10

50 10

9

≤85°C ≤125°C Unit

65 13 11

95 19 16

5 5 5

65 13 11

75 15 13

65 13 11

75 15 13

110

22 19

5 5 5

75 15 13

90 18 15

75 15 13

ns

Tw Minimum Pulse Width, Latch Clock

(Figure 6)

tr, tf Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

2.0

4.5

6.0

50 10

9

1000

500 400

65 13 11

1000

500 400

75 15 13

1000

500 400

ns

SLS

System Logic

SL74HC595

Semiconductor

FUNCTION TABLE

Inputs Resulting Function

Operation Reset Serial

Input

Reset shift register L X X L,H,

Shift data into shift register

Shift register remains unchanged

Transfer shift register contents to latch register

Latch register remains unchanged

Enable parallel outputs

Force outputs into high-impedance state

SR = shift register contents X = don’t care LR = latch register contents Z = high impedance D = data (L,H) logic level * = depends on Reset and Shift Clock inputs U = remains unchanged ** = depends on Latch Clock input

H D L,H, L D SRA

H X L,H, L,H, L U U U U

H X L,H, L U SRN LRN U SRN

X X X L,H, L * U * U

X X X X L * ** * Enabled

X X X X H * ** * Z

A

Shift

Clock

Latch Clock

Output

Enable

L L U L U

Shift

Register

Contents

SRN SR

N+1

Latch

Register

Contents

U SRG SRH U

Serial

Output

SQH

Parallel

Outputs

QA-QH

PIN DESCRIPTIONS

INPUTS:

A - Serial Data Input. The data on this pin is shifted

into the 8-bit serial shift register.

CONTROL INPUTS: Shift Clock - Shift Register Clo ck Input. A low-to-

high transition on this input causes the data at the Serial Input pin to be shifted into the 8-bit shift register.

Reset - Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected.

System Logic

SLS

Latch Clock - Storage Latch Clock Input. A low-tohigh transition on this input latches the shift register data.

Output Enable - Active-Low Output Enable. A low on this input allows the data from the latches to bepresented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance state. The serial output is not affected by this control unit.

OUTPUTS:

QA-QH - Noninverted, 3-state, latch outputs. SQH - Voninverted, Serial Data Output. This is the

output of the eighth stage of the 8-bit shift register. This output does not have three-state capability.

SL74HC595

Semiconductor

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms Figure 4. Switching Waveforms

Figure 5. Switching Waveforms Figure 6. Switching Waveforms

Figure 7. Test Circuit Figure 8. Test Circuit

SLS

System Logic

SL74HC595

Semiconductor

TIMING DIAGRAM

SLS

System Logic

SL74HC595

Semiconductor

EXPANDED LOGIC DIAGRAM

SLS

System Logic