Page 1
SL74HC533
Semiconductor
Octal 3-State Inverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC533 is identical in pinout to the LS/ALS533. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting
the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches,
but when Output Enable is high, all device outputs are forced to the
high-impedance state. Thus, data may be latched even when the
outputs are not enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC533N Plastic
SL74HC533D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs Output
Output
Enable
L H H L
L H L H
L L X no
H X X Z
X = don’t care
Z = high impedance
Latch
Enable
D Q
change
SLS
System Logic
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SL74HC533
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
V
=6.0 V
CC
0
1000
0
0
500
400
mW
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
SL74HC533
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VIN=VIH or VIL
VOL Maximum Low -Level
Output Voltage
VIN=VIH or VIL
IIN Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
I
≤ 6.0 mA
OUT
I
≤ 7.8 mA
OUT
VIN= VIL or VIH
I
≤ 20 µA
OUT
I
≤ 6.0 mA
OUT
I
≤ 7.8 mA)
OUT
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Leakage Current
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
Unit
V
V
V
V
IOZ Maximum Three-State
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
Output in High-Impedance
State
VIN= V
V
IL
OUT=VCC
or V
IH
or GND
VIN=VCC or GND
I
=0µA
OUT
6.0 ±0.5 ±5.0 ±10 µA
6.0 8.0 80 160 µA
System Logic
SLS
Page 4
SL74HC533
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF,Input tr=tf=6.0 ns)
L
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
t
t
t
t
PLH
PLH
PLZ
PZL
TLH
Maximum Propagation Delay, Input D to Q
PHL
(Figures 1 and 5)
, t
Maximum Propagation Delay, Latch Enable to Q
PHL
(Figures 2 and 5)
, t
Maximum Propagation Delay , Output Enable to Q
PHZ
(Figures 3 and 6)
, t
Maximum Propagation Delay , Output Enable to Q
PZH
(Figures 3 and 6)
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 5)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
175
35
30
175
35
30
150
30
26
150
30
26
60
12
10
220
44
37
220
44
37
190
38
33
190
38
33
75
15
13
265
53
45
265
53
45
225
45
38
225
45
38
90
18
15
CIN Maximum Input Capacitance - 10 10 10 pF
ns
ns
ns
ns
ns
C
Maximum Three-State Output Capacitance
OUT
- 15 15 15 pF
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
TIMING REQUIREMENTS(C
2
f+ICCVCC
CC
=50pF,Input tr=tf=6.0 ns)
L
37 pF
VCC Guaranteed Limit
Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit
tsu Minimum Setup Time, Input D to
Latch Enable (Figure 4)
th Minimum Hold Time, Latch Enable to
Input D(Figure 4)
tw Minimum Pulse Width, Latch Enable
(Figure 2)
tr, tf Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
75
15
13
5
5
5
80
16
14
1000
500
400
95
19
16
5
5
5
100
20
17
1000
500
400
110
22
19
5
5
5
120
24
20
1000
500
400
ns
ns
ns
ns
SLS
System Logic
Page 5
SL74HC533
Semiconductor
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Test Circuit Figure 6. Test Circuit
SLS
System Logic
Page 6
SL74HC533
Semiconductor
EXPANDED LOGIC DIAGRAM
SLS
System Logic
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