Page 1
Semiconductor
Octal 3-State Noninverting Buffer/Line
Driver/Line Receiver
High-Performance Silicon-Gate CMOS
The SL74HC241 is identical in pinout to the LS/ALS241. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers, and
other bus-oriented systems. The device has noninverting outputs and
two output enables. Enable A is active-low and Enable B is active-high.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC241N Plastic
SL74HC241D SOIC
TA = -55° to 125° C for all packages
SL74HC241
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output Inputs Output
Enable A A YA Enable B B YB
L L L H L L
L H H H H H
H X Z L X Z
SLS
X = don’t care
Z = high impedance
System Logic
Page 2
SL74HC241
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±35 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
V
=6.0 V
CC
0
0
0
1000
500
400
mW
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
SL74HC241
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-
Level Input
Voltage
VIL Maximum Low -
Level Input
Voltage
VOH Minimum High-
Level Output
Voltage
VIN= VIH
VOL Maximum Low -
Level Output
Voltage
VIN= VIL
IIN Maximum Input
V
= VCC-0.1 V
OUT
I
≤ 20 µA
OUT
V
= 0.1 V
OUT
I
≤ 20 µA
OUT
VIN= VIH
I
≤ 20 µA
OUT
I
≤ 6.0 mA
OUT
I
≤ 7.8 mA
OUT
VIN = VIL
I
≤ 20 µA
OUT
I
≤ 6.0 mA
OUT
I
≤7.8 mA
OUT
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Leakage Current
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
Unit
V
V
V
V
IOZ Maximum three
State Leakage
Current
ICC Maximum
Quiescent Supply
Current
(per Package)
System Logic
SLS
Output in High-Impedance State
VIN = VIL or V
V
OUT=VCC
IH
or GND
VIN=VCC or GND
I
=0µA
OUT
6.0 ±0.5 ±5.0 ±10.0 µA
6.0 4.0 40 160 µA
Page 4
SL74HC241
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF,Input tr=tf=6.0 ns)
L
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
t
t
t
PLH
PLZ
PZH
TLH
Maximum Propagation Delay, A to YA or B to YB
PHL
(Figures 1 and 3)
, t
Maximum Propagation Delay, Output Enable to
PHZ
YA or YB (Figures 2 and 4)
, t
Maximum Propagation Delay, Output Enable to
PZL
YA or YB (Figures 2 and 4)
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 3)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
90
18
15
110
22
19
110
22
19
60
12
10
115
23
20
140
28
24
140
28
24
75
15
13
135
27
23
165
33
28
165
33
28
90
18
15
CIN Maximum Input Capacitance - 10 10 10 pF
C
Maximum Three-State Output Capacitance
OUT
- 15 15 15 pF
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Transceiver
Typical @25°C,VCC=5.0 V
Channel)
ns
ns
ns
ns
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
2
f+ICCVCC
CC
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
34 pF
SLS
System Logic
Page 5
SL74HC241
Semiconductor
Figure 3. Test Circuit Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
SLS
System Logic
Loading...