Page 1
Semiconductor
8-Input Data Selector/Multiplexer
High-Performance Silicon-Gate CMOS
The SL74HC151 is identical in pinout to the LS/ALS151. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Strobe pin must be at a low
level for the sele cted data to appear at the outputs. If Strobe is high,
the Y output is forced to a low level and the Y output is forced to a
high level.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
SL74HC151
ORDERING INFORMATION
SL74HC151N Plastic
SL74HC151D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
A2 A1 A0 Strobe Y Y
X X X H L H
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
SLS
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
D0,D1...D7=the level of the respective D
input
X = don’t care
System Logic
Page 2
SL74HC151
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±25 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Ai r, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond whi ch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
V
=6.0 V
CC
0
1000
0
0
500
400
mW
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
System Logic
SLS
Page 3
SL74HC151
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VIN=VIH or VIL
VOL Maximum Low -Level
Output Voltage
VIN=VIH or VIL
IIN Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
I
≤ 20 µA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
I
≤ 4.0 mA
OUT
I
≤ 5.2 mA
OUT
VIN=VIH or VIL
I
≤ 20 µA
OUT
I
≤ 4.0 mA
OUT
I
≤ 5.2 mA
OUT
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Leakage Current
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
Unit
V
V
V
V
ICC Maximum Quiescent
Supply Current
(per Package)
System Logic
SLS
VIN=VCC or GND
I
=0µA
OUT
6.0 8.0 80 160 µA
Page 4
SL74HC151
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF,Input tr=tf=6.0 ns)
L
VCC Guaranteed Limit
Symbol Parameter V 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
t
t
t
PLH
PLH
PLH
TLH
Maximum Propagation Delay, Input D to
PHL
Output Y or Y (Figures 1,3 and 6)
, t
Maximum Propagation Delay , Input A to
PHL
Output Y or Y (Figures 2 and 6)
, t
Maximum Propagation Delay , Strobe to
PHL
Output Y or Y (Figures 4,5 and 6)
, t
Maximum Output Transition Time, Any Output
THL
(Figures 1 and 6)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
185
37
31
205
41
35
125
25
21
75
15
13
230
46
39
255
51
43
155
31
26
95
19
16
280
56
48
310
62
53
190
38
32
110
22
19
CIN Maximum Input Capacitance - 10 10 10 pF
Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDV
2
f+ICCVCC
CC
36 pF
ns
ns
ns
ns
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
System Logic
SLS
Page 5
SL74HC151
Semiconductor
Figure 5. Switching waveforms Figure 6.Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Loading...