Page 1
Semiconductor
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
The SL4516B Presettable Binary Up/Down Counter consists of four
synchronously clocked D-type flip-flops (with a gating structure to
provide T-type flip-flop capability) connected as counters. This
counter can be cleared by a high level on the RESET line, and can be
preset to any binary number present on the jam inputs by a high level
on the PRESET ENABLE line.
If the CARRY-IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous cascading
is accomplished by connecting all clock inputs in parallel and
connecting the CARRY -OUT of a less significant stage to the CARRYIN of a more significant stage.
The SL4516B can be cascaded in the ripple mode by connecting the
CARRY -OUT to the clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY-OUT must be gated with
the clock, and the UP/DOWN input must change while the clock
is high. This method provides a clean clock signal to the
subsequent counting stage.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
SL4516B
ORDERING INFORMATION
SL4516BN Plastic
SL4516BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
SLS
LOGIC DIAGRAM
System Logic
PIN 16=VCC
PIN 8= GND
FUNCTION TABLE
Inputs Outputs
CL CI U/D PE R Mode
X H X L L NO COUNT
L H L L COUNT UP
L L L L COUNT
DOWN
X X X H L PRESET
X X X X H RESET
X = don’t care
Page 2
SL4516B
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V
VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±10 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor 100 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
750
500
260 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 3.0 18 V
VIN, V
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
mW
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
OUT
)≤VCC.
should be constrained to the range
OUT
System Logic
SLS
Page 3
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
SL4516B
Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125
°C
VIH Minimum High-Level
Input Voltage
VIL Maximum Low -Level
Input Voltage
VOH Minimum High-Level
Output Voltage
VOL Maximum Low -Level
Output Voltage
IIN Maximum Input
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
V
= 0.5 V or V
OUT
V
= 1.0 V or V
OUT
V
= 1.5 V or V
OUT
VIN=GND or VCC 5.0
VIN=GND or VCC 5.0
- 0.5V
CC
- 1.0 V
CC
- 1.5V
CC
- 0.5V
CC
- 1.0 V
CC
- 1.5V
CC
5.0
10
15
5.0
10
15
10
15
10
15
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA
Leakage Current
ICC Maximum Quiescent
Supply Current
(per Package)
IOL Minimum Output Low
(Sink) Current
VIN= GND or VCC 5.0
10
15
20
VIN= GND or VCC
UOL=0.4 V
UOL=0.5 V
UOL=1.5 V
5.0
10
15
5
10
20
100
0.64
1.6
4.2
5
10
20
100
0.51
1.3
3.4
150
300
600
3000
0.36
0.9
2.4
Unit
V
V
V
V
µA
mA
IOH Minimum Output High
(Source) Current
System Logic
SLS
VIN= GND or VCC
UOH=2.5 V
UOH=4.6 V
UOH=9.5 V
UOH=13.5 V
5.0
5.0
10
15
-2
-0.64
-1.6
-4.2
-1.6
-0.51
-1.3
-3.4
-1.15
-0.36
-0.9
-2.4
mA
Page 4
SL4516B
Semiconductor
AC ELECTRICAL CHARACTERISTICS(C
=50pF, RL=200kΩ, Input tr=tf=20 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
t
, t
t
t
t
t
t
PHL
PHL
PHL
PHL
PHL
THL
Maximum Propagation Delay, Clock to Q (Figure
PLH
1)
, t
Maximum Propagation Delay, Preset or Reset to
PLH
Q (Figure 1)
, t
Maximum Propagation Delay, Clock to Carry Out
PLH
(Figure 1)
, t
Maximum Propagation Delay, Carry In to Carry
PLH
Out (Figure 1)
, t
Maximum Propagation Delay, Preset or Reset to
PLH
Carry Out (Figure 1)
, t
Maximum Output Transition Time, Any Output
TLH
(Figure 1)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
400
200
150
420
210
160
480
240
180
250
120
100
640
320
250
200
100
80
400
200
150
420
210
160
480
240
180
250
120
100
640
320
250
200
100
80
800
400
300
840
420
320
960
480
360
500
240
200
1280
640
500
400
200
160
ns
ns
ns
ns
ns
ns
CIN Maximum Input Capacitance - 7.5 pF
TIMING REQUIREMENTS(C
=50pF, RL=200 kΩ, Input tr=tf=20 ns)
L
VCC Guaranteed Limit
Symbol Parameter V ≥-55°C 25°C ≤125°C Unit
tsu Minimum Setup Time, P to Preset Enable
(Figure 1)
tsu Minimum Setup Time, Up/Down to Clock
(Figure 1)
5.0
10
15
5.0
10
25
10
10
25
10
10
50
20
20
ns
15
tsu Minimum Setup Time, Carry In to Clock
(Figure 1)
5.0
10
ns
15
th Minimum Hold Time, Clock to Carry In (Figure 1) 5.0
10
15
th Minimum Hold Time, Clock to Up/Down (Figure
1)
5.0
10
15
60
30
30
30
30
30
60
30
30
30
30
30
120
60
60
60
60
60
ns
ns
ns
th Minimum Hold Time, Preset enable to P (Figure
1)
5.0
10
70
40
70
40
SLS
140
ns
80
System Logic
Page 5
SL4516B
Semiconductor
15 40 40 80
Figure 1. Switching Waveforms
TIMING DIAGRAM
SLS
System Logic
Page 6
SL4516B
Semiconductor
EXPANDED LOGIC DIAGRAM
System Logic
SLS
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